Cldrv - Intel 82496 CACHE CONTROLLER User Manual

HARDWARE INTERFACE
5.2.2.34.
CLDRV
ClDRV 82491 Cache SRAM Cache low Drive
Selects 82496 Cache Controller output driving buffers for 82491 Cache SRAM
signals.
Configuration Input to 82496 Cache Controller (pin N04)
Synchronous to ClK
Signal Description
CLDRV selects the driving strength of the 82496 Cache Controller buffers that interface to the
82491 Cache SRAM.
When Sampled
CLDRV is a configuration input which is sampled as shown in the Initialization and
Configuration chapter. The 82496 Cache Controller to 82491 Cache SRAM control signals
(BLAST#, BLEC#, BUS#, MAWEA#, MCYC#, WAY, WBA[SEC2#], WBTYP[LRO],
WBWE#[LRl], WRARR#) can be configured for one of two buffers. The buffer selection is
made by using the CLDRV configuration input. CLDRV must be driven by the MBC to the
value shown in Table 4-7 for at least 10 CPU clocks prior to the falling edge of RESET.
After it is sampled, CLDRV is a "don't care" signal until after CADS# is asserted for the first
time, when it becomes the BGT# pin.
Relation to Other Signals
Pin Symbol
Relation to Other Signals
RESET
ClDRV is sampled when RESET is active. Refer to Chapter 4 for specific timing
requirements with respect to RESET.
BGT# ClDRV shares a pin with BGT#.
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