Intel 82496 CACHE CONTROLLER User Manual page 96

COMPONENT OPERATION
• RNRM:
82496 Cache Controller Read Normal Cycle: This is a normal read cycle which
will be executed by the 82496 Cache Controller for non-cacheable accesses.
• SRUP:
82491 Cache SRAM SRAM update. This cycle occurs any time new information is
placed in the 82491 Cache SRAM cache. An SRAM update is implied in the
LFIL
cycle.
• ALLOC:
82496 Cache Controller allocation. This cycle is a linefill that results from a
cacheable write miss cycle.
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