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Intel 80331 Design Manual

Intel 80331 Design Manual

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Intel
80331 I/O Processor
Design Guide
March 2005
Order
Number:273823-003

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  • Page 1 ® Intel 80331 I/O Processor Design Guide March 2005 Order Number:273823-003...
  • Page 2 States and other countries. The ARM* and ARM Powered logo marks (the ARM marks) are trademarks of ARM, Ltd., and Intel uses these marks under license from ARM, Ltd.î *Other names and brands may be claimed as the property of others.

  • Page 3: Table Of Contents

    6.1.2 PCI Resistor Compensation ..................42 PCI General Layout Guidelines ..................43 PCI-X Topology Layout Guidelines..................43 ® Intel 80331 I/O Processor PCI/X Layout Analysis ............44 6.4.1 PCI Clock Layout Guidelines .................45 6.4.2 Single-Slot at 133 MHz ..................48 6.4.3 Embedded PCI-X 133 MHz ...................49 6.4.4...
  • Page 4 6.4.19 PCI 33 MHz Mixed Topology ................. 65 Memory Controller........................67 DDR Bias Voltages ......................67 ® Intel 80331 I/O Processor DDR Overview ................ 68 DDR 333 Signal Integrity Simulation Conditions ..............69 7.3.1 DDR 333 Stackup Example ................... 70 DDR Layout Guidelines ...................... 72 7.4.1...
  • Page 5 Intel® 80331 I/O Processor Design Guide Contents Battery Backup .........................134 9.3.1 Non-Battery Backup Circuits................135 ® Intel IQ80331 Evaluation Platform Board ................137 JTAG Circuitry for Debug ......................139 11.1 Requirements ........................139 11.2 JTAG Signals / Header .....................140 11.3 System Requirements ......................141 11.4 JTAG Hardware Requirements..................142...
  • Page 6 80331 I/O Processor Preliminary Ballout (Bottom View) ..........20 ® Intel 80331 I/O Processor Power Plane Layout................ 21 ® Intel 80331 I/O Processor PCI-X Adapter Card Block Diagram ..........22 Configuration........................27 CCPLL ® Intel 80331 I/O Processor DDRRES Resistor Compensation Circuitry ........28 DDR Driver Compensation Circuitry ...................
  • Page 7 Intel® 80331 I/O Processor Design Guide Contents ® Intel 80331 I/O Processor DDRII 400 DIMM Source Synchronous Routing......104 50 DDR II 400 DIMM DQ Topology ....................106 51 DDR II 400 DIMM DQS Topology.....................106 52 DDR II 400 DIMM Clock Topology....................107 53 DDR II 400 DIMM Address/CMD Topology ................109...
  • Page 8 Intel® 80331 I/O Processor Design Guide Contents Tables Terminology and Definitions ....................... 12 FC-style, H-PBGA Package Dimensions..................17 Terminations: Pull-up/Pull-down ....................23 Decoupling Recommendations....................34 Motherboard Stack Up, Stripline and Microstrip ................. 37 Adapter Card Stack Up, Microstrip and Stripline ................ 39 PCI-X Slot Guidelines.........................
  • Page 9 Intel® 80331 I/O Processor Design Guide Contents 49 Embedded DDR 333 Buffered Clock Topology Lengths ............94 50 Embedded DDR 333 Unbuffered Clock Topology Lengths ............95 51 DDR 333 Embedded Address/Command Routing Recommendations ........96 52 Embedded DDR 333 Unbuffered Address/CMD Topology Lengths...........98 53 Embedded DDR 333 Registered Address/CMD Topology Lengths ...........99...

  • Page 10: Revision History

    This is required only for unbuffered clocks and was already mentioned in the previous row. Table 51: removed row in “Trace Length: 80331 signal Ball to Series Termination” because the series termination is no longer needed. October 2004...

  • Page 11: Introduction

    Designers please note that this guide focuses upon specific design considerations for the 80331 and is not intended to be an all-inclusive list of all good design practices. Use this guide as a starting point and use empirical data to optimize your particular design.

  • Page 12: Terminology And Definitions

    Intel® 80331 I/O Processor Design Guide Introduction 1.1.1 Terminology and Definitions Table 1. Terminology and Definitions (Sheet 1 of 2) Term Definition ® 80331 Intel 80331 I/O processor Stripline in a PCB is composed of the conductor inserted in a dielectric with GND planes to the top and bottom.
  • Page 13 Outbound At or toward the PCI interface of the 80331 ATU from the Internal Bus. Inbound At or toward the Internal Bus of the 80331 from the PCI interface of the ATU. ® Local processor Intel XScale core within the 80331 ®...

  • Page 14: Other Relevant Documents

    Intel® 80331 I/O Processor Design Guide Introduction 1.1.2 Other Relevant Documents 1. Intel 80331 I/O Processor Specification Update (273930), Intel Corporation ® ® 2. Intel 80331 I/O Processor Datasheet (273943), Intel Corporation ® 3. Intel 80331 I/O Processor Developer’s Manual (...

  • Page 15: About The Intel ® 80331 I/O Processor

    Introduction ® About the Intel 80331 I/O Processor ® The 80331 is a multi-function device that integrates the Intel XScale core (ARM* architecture compliant) with intelligent peripherals and PCI-to-PCI Bridge. The 80331 consolidates the following into a single system: ®...
  • Page 16 Intel® 80331 I/O Processor Design Guide Introduction Figure 1 provides a block diagram of the 80331. ® Figure 1. Intel 80331 I/O Processor Functional Block Diagram 16-bit UART 2 - 1²C 32/64-bit DDR ® Intel XScale™ Units Units Interface Core...

  • Page 17: Package Information

    Intel® 80331 I/O Processor Design Guide Package Information Package Information The 80331 is offered in a Flip Chip Ball Grid Array (FCBGA) package. This is a full-array package with 829 ball connections. The mechanical dimensions for this package are provided in the figure below and...

  • Page 18: Intel ® 80331 I/O Processor 829-Ball Fcbga Package Diagram

    ® Figure 2. Intel 80331 I/O Processor 829-Ball FCBGA Package Diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29...
  • Page 19 Intel® 80331 I/O Processor Design Guide Package Information ® Figure 3. Intel 80331 I/O Processor Preliminary Ballout (Top View) DDR/DDRII/SDRAM GPIO JTAG VCC/VSS Secondary Primary PCI-X Bus PCI-X Bus B1758-01...

  • Page 20: Intel ® 80331 I/O Processor Preliminary Ballout (Bottom View)

    Package Information ® Figure 4. Intel 80331 I/O Processor Preliminary Ballout (Bottom View) 1 0 1 1 1 2 1 3 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4...

  • Page 21: Power Plane Layout

    Intel® 80331 I/O Processor Design Guide Package Information Power Plane Layout Figure 5 provides an example of how the 80331 DDR, CPU core and 1.5 V core power planes are ® partitioned on the Intel IQ80331 Evaluation Platform Board (IQ80331).

  • Page 22: Intel ® 80331 I/O Processor Applications

    Intel 80331 I/O Processor Applications This section provides a block diagram of a 80331 Serial ATA adapter card application. This entire SATA RAID card adapter can be implemented with just a few chips using the 80331 integrated PCI-X bridge and IO processing capability.

  • Page 23: Terminations

    Intel® 80331 I/O Processor Design Guide Terminations Terminations This chapter provides the recommended pull-up and pull-down terminations for a 80331 layout. Table 3 lists these 80331 termination values. On a motherboard, the PCI Local Bus Specification, Revision 2.3 requires that the PCI signals provide the termination resistors. Pull-ups on the PCI signals are not required with PCIODT_EN = 1 (enabled), because they are implemented on the die.
  • Page 24 S_ACK64#, S_FRAME#, S_IRDY#, S_DEVSEL#, S_TRDY#, S_STOP#, S_PERR#, S_LOCK#, S_M66EN, S_SERR# and XINT[3:0]# NOTE: This signal is muxed onto signal A[20]. Primary PCI-X Bus Width: By default, identifies 80331 subsystem as 64-bit unless user attaches appropriate pull-down resistor. 1.5 K pull-down when P_32BITPCI# 0 = 32 bit wide bus.
  • Page 25 133 MHz PCI-X: use 0.01 µF to GND. Private Memory Enable: PRIVMEM latched at rising (deasserting) edge of P_RST# and determines when the 80331 operates with Private Memory Space on the secondary PCI bus of the PCI-to-PCI 1.5 K pull-down when Bridge.
  • Page 26 0 = Hold in reset. (Requires pull-down resistor.) 1 = Do not hold in reset. (Default mode) Muxed onto signal AD[5] Bridge Enable: BRG_EN latched at rising (deasserting) edge of P_RST# and determines when the 80331 operates with PCI-to-PCI Bridge. 1.5 K pull-down when BRG_EN 0 = Disable Bridge, enable P_CLK input on S_CLKIN input.

  • Page 27: Analog Filters

    Intel® 80331 I/O Processor Design Guide Terminations Analog Filters The following section describes filters needed for biasing PLL circuitry. 3.1.1 Pin Requirements CCPLL To reduce clock skew, the V balls for the Phase Lock Loop (PLL) circuit are isolated on the CCPLL package.

  • Page 28: Ddr Resistor Compensation

    Terminations DDR Resistor Compensation Figure 8 provides the 80331 DDR II DDRES circuitry. The DDRRES1 resistor has a tight tolerance of 40.2 ohm 0.5%. DDRRES2 is used as compensation for DDR-II OCD. Due to the fact that OCD is not supported this pin should be pulled to GND with a 1K resistor.

  • Page 29: Ddr Driver Compensation

    Intel® 80331 I/O Processor Design Guide Terminations DDR Driver Compensation External reference resistors are used to control slew rate and driver impedance. The DDRIMPCRES (or DDRDRVCRES) resistor directly controls the on-die termination (ODT). The recommendations are as follows: • DDRIMPCRES: controls on-die termination, DDR - 385 ohms, DDRII - 285 ohms. Note that the closest standard 1% resistors are acceptable •...
  • Page 30 Intel® 80331 I/O Processor Design Guide Terminations This Page Intentionally Left Blank...

  • Page 31: Routing Guidelines

    In fact, it is highly recommended that the board design be simulated to determine optimum layout for signal integrity. The information in this chapter provides guidelines to aid the designer with board layout. Several factors influence the signal integrity of a 80331 design. These factors include: •...

  • Page 32: Crosstalk

    Intel® 80331 I/O Processor Design Guide Routing Guidelines Crosstalk Crosstalk is caused by capacitive and inductive coupling between signals. Crosstalk is composed of both backward and forward crosstalk components. Backward crosstalk creates an induced signal on victim network that propagates in the opposite direction of the aggressor signal. Forward crosstalk creates a signal that propagates in the same direction as the aggressor signal.

  • Page 33: Pcb Ground Layout Around Connectors

    Intel® 80331 I/O Processor Design Guide Routing Guidelines Figure 11. PCB Ground Layout Around Connectors Connector Connector Pins GND PCB Layer A. Incorrect method B. Correct method A9260-01...

  • Page 34: Emi Considerations

    Intel® 80331 I/O Processor Design Guide Routing Guidelines EMI Considerations It is highly recommended that good EMI design practices be followed when designing with the 80331. • To minimize EMI on your PCB a useful technique is to not extend the power planes to the edge of the board.
  • Page 35 Intel® 80331 I/O Processor Design Guide Routing Guidelines Table 4. Decoupling Recommendations Number of Voltage Plane Voltage Pins Package C (µF) Caps DDR/DDRII 2.5/1.8V VCC25/18 1210 DDR/DDRII 2.5/1.8V VCC25/18 7343 Core 1.5V VCC15 0603 Core 1.5V VCC15 1210 1.35V VCC13 0603 1.35V...

  • Page 36: Trace Impedance

    Intel® 80331 I/O Processor Design Guide Routing Guidelines Trace Impedance All signal layers require controlled impedance of 50 Ω +/- 15%, microstrip or stripline where appropriate for motherboard applications and 60 Ω +/- 15%, microstrip or stripline, for add-in card applications.

  • Page 37: Board Layout Guidelines

    Motherboard Stack Up Information When 80331 is used in server and workstation Raid On Mother Board (ROMB) applications the motherboard is implemented on eight layers. The specified impedance range for all board implementations are 50 ohms +/-15%. Adjustments are made for interfaces specified at other impedances.

  • Page 38: Motherboard Stackup Recommendations

    Intel® 80331 I/O Processor Design Guide Board Layout Guidelines Table 5. Motherboard Stack Up, Stripline and Microstrip (Sheet 2 of 2) Nominal Minimum Maximum Variable Type Notes (mils) (mils) (mils) Stripline Microstrip 15.0 Each interface sets the trace spacing based on its signal integrity of differential impedance requirements.

  • Page 39: Adapter Card Stackup

    Board Layout Guidelines Adapter Card Stackup The 80331 can be implemented on PCI-X adapter cards with six or eight layer stackups. The specified impedance range for all adapter card implementations are 60ohms +/-15%. Adjustments are made for interfaces specified at other impedances.

  • Page 40: Adapter Card Stackup

    Intel® 80331 I/O Processor Design Guide Board Layout Guidelines Figure 13. Adapter Card Stackup Microstrip Trace Spacing Microstrip Microstrip Trace Thickness Trace Width Solder Mask Thickness Trace Height 1 L2 (GND) Trace Height 2 Stripline Trace Thickness Trace Height 3...

  • Page 41: Pci-X Layout Guidelines

    Interrupt Routing and IDSEL Lines Figure 14 shows the 80331 connected to three PCI connectors. Notice that the interrupts are rotated for each connector. The practice of Rotating INTs can also be used when connecting to individual multifunction PCI devices as well. The IDSEL lines acts as chip selects during the configuration cycles.

  • Page 42: Pci Arbitration

    6.1.1 PCI Arbitration 80331 contains two PCI Arbiters to facilitate arbitration on the primary and secondary PCI buses. Refer to the PCI Local Bus Specification, Revision 2.3, for more information on arbiter algorithms. The specification essentially states that the algorithm needs to be fair to prevent any one device from consuming to much of the PCI bandwidth.

  • Page 43: Pci General Layout Guidelines

    Intel® 80331 I/O Processor Design Guide PCI-X Layout Guidelines PCI General Layout Guidelines For acceptable signal integrity with bus speeds up to 133 MHz it is important to PCB design layout to have controlled impedance. • Signal trace velocity needs to be roughly 150 – 190 ps/inch •...

  • Page 44: Intel ® 80331 I/O Processor Pci/X Layout Analysis

    Intel® 80331 I/O Processor Design Guide PCI-X Layout Guidelines ® Intel 80331 I/O Processor PCI/X Layout Analysis The following sections describe layout recommendations based on the signal integrity simulation analysis. This analysis was conducted using the following parameters: • System board stack up: 50 ohm +/- 15% single-ended impedance •...

  • Page 45: Pci Clock Layout Guidelines

    The recommended clock buffer layout are specified as follows: • Match each of the 80331 output clock lengths to within 25 mils to help minimize the skew. • Keep distance between clock lines and other signals “d” at least 25 mils from each other.

  • Page 46: Pci-X Clock Layout Requirements Summary

    CLKOUT to CLKIN) should be routed 3.5” longer than the Clocks running to the Slots. This should be done to a tolerance of within 25 mills. Total Length of 80331 PCI CLKs on a Less than 14.0” maximum. motherboard (or embedded design).
  • Page 47 Intel® 80331 I/O Processor Design Guide PCI-X Layout Guidelines Table 8. PCI-X Clock Layout Requirements Summary (Sheet 2 of 2) Parameter Routing Guidelines Maximum skew for PCI. 1.0 ns. Point-to-point signal routing needs to be used to keep reflections Routing Guideline 1.

  • Page 48: Single-Slot At 133 Mhz

    6.4.2 Single-Slot at 133 MHz Figure 17 shows one of the chipset PCI AD lines connected through TL_AD1 line segments to a single-slot connector CONN1 through TL1 line segment to the 80331. Figure 17. Single-Slot Point-to-Point Topology CONN1 Table 9.

  • Page 49: Embedded Pci-X 133 Mhz

    Intel® 80331 I/O Processor Design Guide PCI-X Layout Guidelines 6.4.3 Embedded PCI-X 133 MHz This section lists the routing recommendations for PCI-X 133 MHz without a slot. Figure 18 shows the block diagram of this topology and Table 10 describes the routing recommendations.

  • Page 50: Embedded Pci-X 133 Mhz Alternate Topology

    Intel® 80331 I/O Processor Design Guide PCI-X Layout Guidelines 6.4.4 Embedded PCI-X 133 MHz Alternate Topology This section lists another embedded topology with routing recommendations for PCI-X 133 MHz. Figure 19 shows the block diagram of this topology and Table 11 describes the routing recommendations.

  • Page 51: Combination Of Pci-X 133 Mhz Slot And Embedded Topology

    Intel® 80331 I/O Processor Design Guide PCI-X Layout Guidelines 6.4.5 Combination of PCI-X 133 MHz Slot and Embedded Topology Figure 20and Table 12 combine the two topologies using both a slot and an embedded device. Figure 20. Embedded PCI-X 133 MHz Topology CONN1 Table 12.

  • Page 52: Combination Pci-X 133 Mhz Slot And Embedded Topology 2

    Intel® 80331 I/O Processor Design Guide PCI-X Layout Guidelines 6.4.6 Combination PCI-X 133 MHz Slot and Embedded Topology 2 Figure 21and Table 13 combine the two topologies using both a slot and an embedded device. Figure 21. Embedded PCI-X 133 MHz Topology CONN1 Table 13.

  • Page 53: Pci-X 100 Mhz Slot Topology

    Intel® 80331 I/O Processor Design Guide PCI-X Layout Guidelines 6.4.7 PCI-X 100 MHz Slot Topology Figure 22and Table 14 provide details on the PCI-X 100 MHz slot topology. Figure 22. Slot PCI-X 100 MHz Slot Routing Topology CONN1 CONN2 Table 14.

  • Page 54: Pci-X 100 Mhz Embedded Topology

    Intel® 80331 I/O Processor Design Guide PCI-X Layout Guidelines 6.4.8 PCI-X 100 MHz Embedded Topology Figure 23and Table 15 combine both a slot and an embedded device. Figure 23. Embedded PCI-X 100 MHz Routing Topology TL_EM1 TL_EM3 TL_EM2 Table 15.

  • Page 55: Pci-X 100 Mhz Slot And Embedded Topology

    Intel® 80331 I/O Processor Design Guide PCI-X Layout Guidelines 6.4.9 PCI-X 100 MHz Slot and Embedded Topology Figure 24and Table 16 combine both slots and an embedded device. Figure 24. Combination of Slot and Embedded PCI-X 100 MHz Routing Topology...

  • Page 56: Pci-X 100 Mhz Slot And Embedded Topology 2

    Intel® 80331 I/O Processor Design Guide PCI-X Layout Guidelines 6.4.10 PCI-X 100 MHz Slot and Embedded Topology 2 Figure 24and Table 16 combine both a slots and an embedded device. Figure 25. Combination of Slots and Embedded PCI-X 100 MHz Routing Topology...

  • Page 57: Pci-X 66 Mhz Slot Topology

    Intel® 80331 I/O Processor Design Guide PCI-X Layout Guidelines Table 17. Combination of Slot and Embedded PCI-X 100 MHz Routing 2 Recommendations (Sheet 2 of 2) Trace Length TL_AD1, TL_AD2 - from connector to 0.75” minimum - 1.5” maximum 1.75” minimum - 2.75” maximum...

  • Page 58: Pci-X 66 Mhz Embedded Topology

    Intel® 80331 I/O Processor Design Guide PCI-X Layout Guidelines Table 18. PCI-X 66 MHz Slot Routing Recommendations (Sheet 2 of 2) Trace Length TL_AD1 to TL_AD4 - from junction to 0.75” minimum - 1.5” maximum 1.75” minimum - 2.75” maximum...

  • Page 59: Pci-X 66 Mhz Mixed Mode Topology

    Intel® 80331 I/O Processor Design Guide PCI-X Layout Guidelines Table 19. PCI-X 66 MHz Embedded Routing Recommendations (Sheet 2 of 2) Microstrip Trace Spacing 18 mils, from edge to edge Group Spacing Spacing from other groups: 25 mils minimum center to center...

  • Page 60: Pci 66 Mhz Slot Topology

    Microstrip Trace Spacing 15 mils, from edge to edge Spacing from other groups: 25 mils minimum Group Spacing edge-to-edge Trace Length 1 TL1: From 80331 signal Ball to first 1.0” minimum - 7.0” 1.0” minimum - 7.0” maximum connector maximum Trace Length TL2 between connectors 0.8”...

  • Page 61: Pci 66 Mhz Embedded Topology

    Intel® 80331 I/O Processor Design Guide PCI-X Layout Guidelines Table 21. PCI 66 MHz Slot Table (Sheet 2 of 2) Routing Guideline for AD Routing Guideline for Parameter Upper AD Bus Trace Length TL_AD1, TL_AD2 from connector to 0.75” minimum - 1.5”...

  • Page 62: Pci 66 Mhz Mixed Mode Topology

    Table 22. PCI 66 MHz Embedded Table (Sheet 2 of 2) Parameter Routing Guideline for AD Bus Trace Length 1 TL1: From 80331 signal Ball to first 5.0” maximum junction Trace Length TL2 between junctions 0.5” minimum - 3.5” maximum Trace Length TL_EM1 to TL_EM4 from junction to 2.0”...

  • Page 63: Pci 33 Mhz Slot Topology

    Microstrip Trace Spacing 15 mils, from edge to edge Group Spacing Spacing from other groups: 25 mils minimum edge-to-edge Trace Length 1 TL1: From 80331 signal Ball to first 1.0” minimum to 5.0” maximum 1.0” minimum - 4.5” maximum connector Trace Length TL_EM1, TL_EM2: From 1st PCI 1.5”...

  • Page 64: Pci 33 Mhz Embedded Mode Topology

    Intel® 80331 I/O Processor Design Guide PCI-X Layout Guidelines Table 24. PCI 33 MHz Slot Routing Recommendations (Sheet 2 of 2) Trace Length TL2 to TL5 0.8” minimum - 1.5” maximum between connectors. Trace Length TL_AD1 to TL_AD5 from connector to 0.75”...

  • Page 65: Pci 33 Mhz Mixed Topology

    Intel® 80331 I/O Processor Design Guide PCI-X Layout Guidelines Table 25. PCI 33 MHz Embedded Routing Recommendations (Sheet 2 of 2) Group Spacing Spacing from other groups: 25 mils minimum edge-to-edge Trace Length 1 TL1: From 80331 signal Ball to first 4.5”...
  • Page 66 PCI 33 MHz Mixed Mode Routing Recommendations (Sheet 2 of 2) Routing Guideline for lower AD Routing Guideline for Parameter upper AD Bus Trace Length 1 TL1: 80331 signal Ball to 1st 1.0” minimum - 5.5” 1.0” minimum - 5.5” maximum junction maximum Trace Length TL2 from 1st junction to 1st PCI 1.5 - 4.0”...

  • Page 67: Memory Controller

    External memory can be configured as host addressable memory or private 80331memory utilizing the Address Translation Unit and Bridge. DDR Bias Voltages The 80331 supports 2.5 V DDR memory and 1.8V for DDRII. Table 27 lists the minimum/maximum values for the DDR memory bias voltages and...

  • Page 68: Intel ® 80331 I/O Processor Ddr Overview

    80331 with the DDR-SDRAM memory sub-system needs continuous ground referencing for all DDR signals. The DDR channel requires the referencing stack-up to allow ground referencing on all of the DDR signals from the 80331 to the parallel termination at the end of the channel. Note: Leave unused M_CKs and M_CK#s unconnected.

  • Page 69: Ddr 333 Signal Integrity Simulation Conditions

    Add-in Card 60 ohm single ended impedance stackup +/- 15% tolerance. • Clock Target Differential Impedance 100 ohms and 50 ohms single-ended impedance. • Memory Model Micron T17A_DQ and Intel generic models. • PLL Clock - Pericom* CDCBV857, PI6DCV16859. •...

  • Page 70: Ddr 333 Stackup Example

    Intel® 80331 I/O Processor Design Guide Memory Controller 7.3.1 DDR 333 Stackup Example Table 31 below provides an example of a table of recommended topologies for motherboard and add-in card eight layer PCB designs. Figure 35 provides an example of a cross section used to implement 100 ohm differential trace impedance.Throughout this section the important...

  • Page 71: Example Topologies For Ddr Trace

    Intel® 80331 I/O Processor Design Guide Memory Controller Table 31. Example Topologies for DDR Trace Min Trace Trace Trace Width Preferred Topology Spacing Impedance Board Type (mils) signals (mils) (ohms) Breakout Motherboard/Add-in Address/ Motherboard/Add-in CMD/Control Microstrip Motherboard/Add-in (layers 1 or 8)

  • Page 72: Ddr Layout Guidelines

    CB, data mask DM, and DQS associated strobe. The 80331 source synchronous signals are divided into groups consisting of data bits DQ and check bits CB. There is an associated strobe DQS for each DQ, DM and CB group. When data masking is not used system memory DM pins on the DDR needs to be tied to ground.

  • Page 73: Routing Requirements

    Intel® 80331 I/O Processor Design Guide Memory Controller 7.4.1.1 Routing Requirements Table 34 Table 35, and Figure 36andFigure 37 show the routing and termination requirements for the source synchronous signal group. Figure 36. Source Synchronous Length Matching Datagroup 1: 8 DQ Lines...

  • Page 74: Source Synchronous Routing Recommendations

    Intel® 80331 I/O Processor Design Guide Memory Controller Table 35. Source Synchronous Routing Recommendations Parameter Routing Guideline Stripline: Route over unbroken ground plane Reference Plane Microstrip Routing: Route over unbroken power or ground plane Preferred Layer Stripline Topology Stripline (stubs needs to be <250 mils)

  • Page 75: Dimm Dq/Dqs Topology Lengths

    Intel® 80331 I/O Processor Design Guide Memory Controller Table 36. DIMM DQ/DQS Topology Lengths Minimum Maximum Trace Traces Description Layer Spacing Notes Length Length Impedance Breakout Microstrip 0.5” 5 mils 45 ohms +/- Lead-in traces are preferred as Lead-in Microstrip 2 “...
  • Page 76 Intel® 80331 I/O Processor Design Guide Memory Controller Table 37. Die to Ball Internal Lengths Signal Lengths Description (mils) DM[6] 805.36 DM[7] 767.5 DM[8] 577.92 DQ[0] 801.6 DQ[1] 801.46 DQ[10] 940.14 DQ[11] 939.24 DQ[12] 939.27 DQ[13] 939.28 DQ[14] 940.03 DQ[15] 940.19...
  • Page 77 Intel® 80331 I/O Processor Design Guide Memory Controller Table 37. Die to Ball Internal Lengths Signal Lengths Description (mils) DQ[4] 800.6 DQ[40] 701.56 DQ[41] 702.02 DQ[42] 701.74 DQ[43] 702.25 DQ[44] 701.86 DQ[45] 702.01 DQ[46] 702.03 DQ[47] 701.93 DQ[48] 806.13 DQ[49] 805.43...
  • Page 78 Intel® 80331 I/O Processor Design Guide Memory Controller Table 37. Die to Ball Internal Lengths Signal Lengths Description (mils) DQS[7] 767.45 DQS[8] 576.94 DQS[0]# 800.66 DQS[1]# 939.23 DQS[2]# 675.03 DQS[3]# 652.62 DQS[4]# 650.75 DQS[5]# 701.68 DQS[6]# 806.15 DQS[7]# 767.44 DQS[8]# 577.9...

  • Page 79: Dimm Dq/Dqs Topology

    Intel® 80331 I/O Processor Design Guide Memory Controller Figure 38. DIMM DQ/DQS Topology V T T 5 1 o h m s + /- 5 % T L 4 T L 1 T L 2 T L 3 2 2 o h m s + /- 5 %...

  • Page 80: Dimm Dq/Dqs Split Termination Topology

    Intel® 80331 I/O Processor Design Guide Memory Controller Table 38. DIMM DQ/DQS Split Termination Topology Lengths Minimum Maximum Trace Traces Description Layer Spacing Notes Length Length Impedance Microstrip/ Breakout 0.5” 5 mils Stripline 45 ohms +/- 15% Lead-in traces are preferred as...

  • Page 81: Clock Signal Groups

    The 80331 drives the command clock in the center of the valid window, and the source-clocked signals propagate with the command clock signal. An important timing specification is the difference between the command clock flight time and the source clocked signal flight time.

  • Page 82: Clock Signal Group Registered/Unbuffered Dimm Routing Requirements

    Intel® 80331 I/O Processor Design Guide Memory Controller Table 40. Clock Signal Group Registered/Unbuffered DIMM Routing Requirements Parameter Routing Guideline Route over unbroken ground plane Reference Plane Differential Microstrip (preferred) or differential Preferred Topology stripline Stripline routing is recommended for the clock signals.

  • Page 83: Ddr 333 Registered Dimm Clock Topology

    Intel® 80331 I/O Processor Design Guide Memory Controller Table 41. Registered DIMM Clock Topology Lengths Minimum Maximum Trace Traces Description Layer Spacing Notes Length Length Impedance 5 mils trace width OK for Breakout Microstrip 0.5” 5 mils breakout. Differential 20 mils...

  • Page 84: Ddr 333 Unbuffered Dimm Clock Topology

    Intel® 80331 I/O Processor Design Guide Memory Controller Table 42. DDR 333 Unbuffered DIMM Clock Topology Lengths Minimum Maximum Trace Traces Description Layer Spacing Notes Length Length Impedance (all 3 5 mils trace width OK for Breakout Microstrip 0.5” 5 mils clock breakout.

  • Page 85: Control Signals Termination

    Intel® 80331 I/O Processor Design Guide Memory Controller 7.4.2.1 Control Signals Termination The control signal group includes RAS#, CAS#, WE#, BA[1:0], MA[12:0] CS[1:0]# , and CKE[1:0]. The series and parallel termination is shown in Table Table 43. Source Clocked Signal Routing...

  • Page 86: Control Signals Routing Guidelines

    Intel® 80331 I/O Processor Design Guide Memory Controller Table 44. Control Signals Routing Guidelines Parameter Routing Guideline Route over unbroken ground plane is preferred. Reference Plane (Refer to Table for alternatives if this is not feasible). Micro-strip only for Un-buffered memory...

  • Page 87: Ddr 333 Dimm Unbuffered/Registered Address/Cmd Topology Lengths

    Intel® 80331 I/O Processor Design Guide Memory Controller Figure 43. DDR 333 DIMM Unbuffered/Registered Address/CMD Topology Lengths VTT (1.25 V) 51 ohms +/- 5% DIMM...

  • Page 88: Control Signal Dimm Topology Lengths

    Intel® 80331 I/O Processor Design Guide Memory Controller Table 45. Control Signal DIMM Topology Lengths Minimum Maximum Traces Description Layer Trace Impedance Spacing Notes Length Length Microstrip 5 mils trace width OK for Breakout 0.5” 5 mils or stripline breakout.

  • Page 89: Embedded Configuration

    Intel® 80331 I/O Processor Design Guide Memory Controller 7.4.3 Embedded Configuration The following tables provide layout guidelines for applications in which the DDR 333 memory SDRAM components are placed directly on the board without a DIMM. 7.4.3.1 DDR 333 Source Synchronous Routine Guidelines This section lists the recommendations for the DDR 333 embedded source synchronous routing.
  • Page 90 Intel® 80331 I/O Processor Design Guide Memory Controller Table 46. DDR 333 Embedded Source Synchronous Routing Recommendations (Sheet 2 of 2) Parameter Routing Guideline 51 ohms +/- 5% • Place the VTT terminations in VTT island after the DIMM (trace length of 0.15” to 0.5”).

  • Page 91: Embedded Ddr 333 Dq/Dqs Topology

    Intel® 80331 I/O Processor Design Guide Memory Controller Figure 44. Embedded DDR 333 DQ/DQS Topology 51 ohms +/- 5% 22 ohms +/- 5% SDRAM Table 47. Embedded DDR 333 DQ/DQS Topology Lengths Minimum Maximum Trace Traces Description Layer Spacing Notes...

  • Page 92: Ddr 333 Embedded Clock Routing Recommendations

    Intel® 80331 I/O Processor Design Guide Memory Controller 7.4.3.2 DDR 333 Embedded Clock Routing Recommendations This section lists the recommendations for the DDR 333 clock signals. Refer to Figure 45 buffered clock topology, Figure 46 for unbuffered clock topology. Refer to...

  • Page 93: Ddr 333 Embedded Registered/Unbuffered Clock Routing Recommendations

    Intel® 80331 I/O Processor Design Guide Memory Controller Table 48. DDR 333 Embedded Registered/Unbuffered Clock Routing Recommendations Parameter Routing Guideline Reference Plane • Route over unbroken ground plane • Stripline routing is recommended for the clock signals. Micro-strip will work with strict adherence Preferred Topology to all routing recommendations.

  • Page 94: Embedded Ddr 333 Buffered Clock Topology Lengths

    Intel® 80331 I/O Processor Design Guide Memory Controller Table 49. Embedded DDR 333 Buffered Clock Topology Lengths Trace Traces Description Layer Spacing Notes Length Length Impedance Microstrip/ Breakout 0.5” 5 mils Differential Routing Stripline Differential 20 mils Microstrip/ Impedance of Lead-in 2”...

  • Page 95: Embedded Ddr 333 Unbuffered Clock Topology

    Intel® 80331 I/O Processor Design Guide Memory Controller Figure 46. Embedded DDR 333 Unbuffered Clock Topology SDRAM SDRAM 120 ohms +/-5% SDRAM 22 ohms +/- 5% 22 ohms +/- 5% SDRAM SDRAM SDRAM Table 50. Embedded DDR 333 Unbuffered Clock Topology Lengths...

  • Page 96: Ddr 333 Embedded Address/Command/Control Routing Guidelines

    Intel® 80331 I/O Processor Design Guide Memory Controller 7.4.3.3 DDR 333 Embedded Address/Command/Control Routing Guidelines This section lists the recommendations for the DDR 333 embedded address/command/control signal routing (RAS#, CAS#, WE#, BA[1:0], MA[12:0] CS[1:0]# CKE[1:0]). Refer to Table 51 Figure 47 for a block diagram of the lengths and matching requirements.
  • Page 97 Intel® 80331 I/O Processor Design Guide Memory Controller Table 51. DDR 333 Embedded Address/Command Routing Recommendations (Sheet 2 of 2) Parameter Routing Guideline • The package lengths from Die to Ball provided in Table 37 must be accounted for when length matching •...

  • Page 98: Embedded Ddr 333 Unbuffered Addr/Cmd Topology

    Intel® 80331 I/O Processor Design Guide Memory Controller Table 52. Embedded DDR 333 Unbuffered Address/CMD Topology Lengths Minimum Maximum Trace Traces Description Layer Spacing Notes Length Length Impedance 45 ohms+/-15% TL1-TL6 as per JEDEC DDR1 Microstrip/ 1.5” 1.67” or 50 ohms...

  • Page 99: Embedded Ddr 333 Registered Address/Cmd Topology Lengths

    Intel® 80331 I/O Processor Design Guide Memory Controller Table 53. Embedded DDR 333 Registered Address/CMD Topology Lengths Minimum Maximum Trace Traces Description Layer Spacing Notes Length Length Impedance Microstrip/ Breakout 0” 0.5” 5 mils 5 mils trace width for breakout...

  • Page 100: Embedded Ddr 333 Registered Addr/Cmd Topology

    Intel® 80331 I/O Processor Design Guide Memory Controller Figure 48. Embedded DDR 333 Registered ADDR/CMD Topology VTT (1.25 V) SDRAM Pin SDRAM Pin 51 ohms +/- 5% TL11 SDRAM Pin SDRAM Pin Register TL10 SDRAM Pin SDRAM Pin SDRAM Pin...

  • Page 101: Ddr Ii 400 Layout Guidelines

    Intel® 80331 I/O Processor Design Guide Memory Controller DDR II 400 Layout Guidelines This section lists the DDRII layout guidelines for both DIMM and embedded designs. The topologies that were analyzed include registered DIMM (RawA and RawB configurations) and embedded single bank configurations (both ECC and Non-ECC type).

  • Page 102: Simulation Conditions

    Clock Target Differential Impedance 100 ohms and 50 ohms single-ended impedance • One Die Termination - ODT value of 75Ω was assumed for all DDR II simulations. • Memory Model Micron U26 and Intel generic models • PLL Clock - ICS ICSU877 •...

  • Page 103: Ddrii-400 Trace Width/Impedance Requirements

    Intel® 80331 I/O Processor Design Guide Memory Controller 7.5.2 DDRII-400 Trace Width/Impedance Requirements Table 57 below provides an example of a table of recommended topologies for motherboard and add-in card eight layer PCB designs. Throughout this section the important recommendation to meet is the trace impedance.

  • Page 104: Dimm Layout Design

    Table 58 for a block diagram of the lengths and matching requirements. ® Figure 49. Intel 80331 I/O Processor DDRII 400 DIMM Source Synchronous Routing DQ Group 1 Y1 +/- 50 mils 8 lines DQS Group 1 DQS# Group 1...

  • Page 105: Ddrii 400 Dimm Source Synchronous Routing Recommendations

    • Spacing from other DQ groups 20 mils minimum • For DQS from any other signals: 20 mils minimum Overall Trace Length: 80331 signal Ball to DIMM 2” minimum to 8” maximum (correlated with the clock connector (no series connector) length from ball to DIMM).

  • Page 106: Ddr Ii 400 Dimm Dqs Lengths

    Intel® 80331 I/O Processor Design Guide Memory Controller Table 59. DDR II 400 DIMM DQ Lengths Spacing Minimum Maximum Trace Traces Description Layer (edge to Notes Length Length Impedance edge) 5 mils trace width OK for Breakout Microstrip 0” 0.5”...

  • Page 107: Ddrii 400 Clock Routing Guidelines

    > 20 mils between other signals. 2.0”min to 10.0” max correlated within the +/- 1.0” of Trace Length 1:80331signal Ball to DIMM connector the DQ/DQS and command signal length (from 80331 to DIMM connector). Length Matching: • Within differential clock signals +/- 0.0250”...

  • Page 108: Ddrii 400 Address/Command/Control Routing Guidelines

    Trace Impedance 45 ohms +/- 15% or 50 ohms +/- 15% 2.0”min to 10” max (Correlated with in +/- 1” of Trace Length: Overall length from 80331 signal Ball to DQ/DQS and command lead-in MB length) DIMM Connector Refer to following table for segment lengths.

  • Page 109: Ddr Ii 400 Dimm Address/Cmd Lengths

    Intel® 80331 I/O Processor Design Guide Memory Controller Table 64. DDR II 400 DIMM Address/CMD Lengths Minimum Maximum Trace Traces Description Layer Spacing Notes Length Length Impedance 5 mils trace width OK for Breakout Microstrip 0” 0.5” 5 mils breakout.

  • Page 110: Embedded Configuration

    Intel® 80331 I/O Processor Design Guide Memory Controller 7.5.4 Embedded Configuration The following tables provide layout guidelines for applications in which the DDRII 400 memory SDRAM, registers and PLL components are placed directly on the board without a DIMM. 7.5.4.1 DDRII 400 Embedded Source Synchronous Routine Guidelines This section lists the recommendations for the DDR II 400 embedded source synchronous routing.

  • Page 111: Ddr Ii 400 Embedded Dq Lengths

    Intel® 80331 I/O Processor Design Guide Memory Controller Table 66. DDR II 400 Embedded DQ Lengths Minimum Maximum Trace Traces Description Layer Spacing Notes Length Length Impedance 5 mils trace width OK for Breakout Microstrip 0” 0.5” 5 mils breakout.

  • Page 112: Ddr Ii 400 Embedded Dqs Lengths

    Intel® 80331 I/O Processor Design Guide Memory Controller Table 67. DDR II 400 Embedded DQS Lengths Minimum Maximum Trace Traces Description Layer Spacing Notes Length Length Impedance 5 mils trace width OK for Breakout Microstrip 0” 0.5” 5 mils breakout.

  • Page 113: Ddrii 400 Embedded Clock Routing Recommendations

    Intel® 80331 I/O Processor Design Guide Memory Controller 7.5.4.2 DDRII 400 Embedded Clock Routing Recommendations This section lists the recommendations for the DDR II 400 clock signals. Refer to Figure 57 Table 68 for a description of the segment lengths and matching requirements...

  • Page 114: Ddr Ii 400 Embedded Clock (Pll) Lengths

    Intel® 80331 I/O Processor Design Guide Memory Controller Table 69. DDR II 400 Embedded Clock (PLL) Lengths Minimum Maximum Trace Traces Description Layer Spacing Notes Length Length Impedance 5 mils trace width OK for Breakout 0” 0.5” 5 mils breakout.

  • Page 115: Ddr Ii 400 Embedded Clock Topology

    Intel® 80331 I/O Processor Design Guide Memory Controller Figure 57. DDR II 400 Embedded Clock Topology Feedback FB_IN TL0_PLLFB TL1_PLLFB Intel® I/O Processor TL2_PLLFB Rp 120 ohms +/- 5% Rp 120 ohms +/- 5% TL0_reg TL0_sdram SDRAM SDRAM Rp 240 ohms...

  • Page 116: Ddrii 400 Embedded Address/Command/Control Routing Guidelines

    • >12 mils within group • >20 mils from any other clock/DQ/DQS groups. 2” minimum - 10” maximum length matched within +/- Overall length 80331 signal Ball to register input 1.0” of target motherboard clock M_CK to PLL. Series Termination none •...

  • Page 117: Ddr Ii 400 Embedded Address/Cmd Lengths

    Intel® 80331 I/O Processor Design Guide Memory Controller Table 71. DDR II 400 Embedded Address/CMD Lengths Minimum Maximum Trace Traces Description Layer Spacing Notes Length Length Impedance 5 mils trace width OK for Breakout 0” 0.5” 5 mils breakout. 45 ohms or •...

  • Page 118: Ddr Ii 400 Embedded Address/Control Topology

    Intel® 80331 I/O Processor Design Guide Memory Controller Figure 58. DDR II 400 Embedded Address/Control Topology SDRAM Pin SDRAM Pin VTT (0.9 V) SDRAM Pin ohms TL10 SDRAM Pin +/- 5% SDRAM Pin Register Intel® I/O Processor SDRAM Pin SDRAM Pin...

  • Page 119: Ddr Ii 400 Embedded Address/Control Topology With Split Termination

    Intel® 80331 I/O Processor Design Guide Memory Controller Figure 59. DDR II 400 Embedded Address/Control Topology With Split Termination SDRAM Pin 1.8 V SDRAM Pin SDRAM Pin ohms TL10 +/- 5% SDRAM Pin ohms +/- 5% SDRAM Pin Register SDRAM Pin...

  • Page 120: Ddr Signal Termination

    Intel® 80331 I/O Processor Design Guide Memory Controller DDR Signal Termination This section provides suggested guidelines for layout of the DDR termination resistors: • Place a 1.25 V termination plane for DDR or a 0.9V termination plane for DDR II 400 on the top layer or one of the inner layers, just beyond the DIMM connector for DDR.

  • Page 121: Ddr Termination Voltage

    Intel® 80331 I/O Processor Design Guide Memory Controller DDR Termination Voltage The V DDR termination voltage must track the V and provide the termination voltage to the termination resistors. This tracking must be 50 percent of (V ) over voltage, temperature, and noise.
  • Page 122 Intel® 80331 I/O Processor Design Guide Memory Controller...

  • Page 123: Peripheral Local Bus

    The Peripheral Bus Interface Unit (PBI) is a data communication path to Flash memory components and peripherals of a 80331 hardware system. The PBI allows the processor to read and write data to these supported flash components and other peripherals. To perform these tasks at high bandwidth, the bus features a burst transfer capability which allows successive 8- or 16-bit data transfers.

  • Page 124: Bus Width

    Intel® 80331 I/O Processor Design Guide Peripheral Local Bus 8.1.3 Bus Width Each address range attributes are programmed in the PBIs boundary registers. The PBI allows an 8-, or 16-bit data bus width for each range. The PBI places 8- and 16-bit data on low-order data signals, simplifying the interface to narrow bus external devices.

  • Page 125: Flash Memory Support

    Intel® 80331 I/O Processor Design Guide Peripheral Local Bus 8.1.4 Flash Memory Support PBI peripheral bus interface supports 8-, or 16- bit Flash devices. The PBI provides programmable wait state functionality for peripheral memory windows. Note: Potentially, programmable wait state functionality could be connected to any peripheral device that has a deterministic wait state profile.

  • Page 126: Layout Guidelines For The Peripheral Bus

    Intel® 80331 I/O Processor Design Guide Peripheral Local Bus 8.1.5 Layout Guidelines for the Peripheral Bus This section provides basic layout guidelines for using the Peripheral Bus. Figures below provide the topology for simulation of clock, control and data lines.

  • Page 127: Topology Layout Guidelines

    Intel® 80331 I/O Processor Design Guide Peripheral Local Bus Topology Layout Guidelines This section provides the topologies for routing the Address/Data bus for single load, latched single load and dual load latched topologies. Note that no length matching is required between the AD lines.

  • Page 128: Routing Guideline Latched Bidirectional Latch Single Load

    Intel® 80331 I/O Processor Design Guide Peripheral Local Bus Figure 65. Peripheral Bus Latched Bidirectional Single Load Topology Flash T L1 Latch Table 74. Routing Guideline Latched Bidirectional Latch Single Load Parameter Routing Guidelines Route over unbroken ground plane or power plane. If...

  • Page 129: Routing Guideline Latch Bidirectional Two Loads

    Intel® 80331 I/O Processor Design Guide Peripheral Local Bus Figure 66. Peripheral Bus Latched Bidirectional Two Load Topology Flash Latch Flash2 Table 75. Routing Guideline Latch Bidirectional Two Loads Parameter Routing Guidelines Route over unbroken ground plane or power plane. If...
  • Page 130 Intel® 80331 I/O Processor Design Guide Peripheral Local Bus This Page Intentionally Left Blank...

  • Page 131: Power Delivery

    0.9V Power Sequencing The 80331 requires that the VCC33 voltage rail be powered up first and then the VCC15. Note that there are no sequence order requirements for the VCC25 or VCC18 rail. The power down sequence is the same in the reverse order.

  • Page 132: Power Failure

    This proposal makes specific assumptions about the system behavior during a power failure. When the below assumptions are not guaranteed, it is the responsibility of the vendor to ensure them. P_RST# is asserted to 80331 when there is at least 2 µs of reliable power remaining. This is •...

  • Page 133: Power Delay

    Intel® 80331 I/O Processor Design Guide Power Delivery In order to trigger a power fail sequence while the IOP power is still valid operating range, a comparator circuit such as the one shown in Figure 67 is recommended. Figure 67.

  • Page 134: Battery Backup

    CKE[1:0] are low. CKE signals will stay low providing the DDR voltage is not removed from 80331. If 80331 is isolated from the DDR battery voltage it is recommended that the CKE circuit shown in Figure 68 be implemented.

  • Page 135: Non-Battery Backup Circuits

    For applications not supporting battery back-up, this circuit not required. When so, follow these steps: • Pull DDR CKE pins high and leave CKE signals on 80331 as ‘no connects’. This keeps SDRAM from entering a pseudo, self-refresh mode, which can cause a lock-up condition on the SDRAM device.
  • Page 136 Intel® 80331 I/O Processor Design Guide Power Delivery This Page Intentionally Left Blank...

  • Page 137: Intel ® Iq80331 Evaluation Platform Board

    IQ80331 Evaluation Platform Board ® The Intel IQ80331 Evaluation Platform Board (80331), also known as the evaluation board, is implemented as a add-in card. This section provides an overview of the IQ80331 features and describes the circuits specific to the IQ80331.

  • Page 138: Four Peaks Customer Reference Board Features

    Intel® 80331 I/O Processor Design Guide ® Intel IQ80331 Evaluation Platform Board Table 77. Four Peaks Customer Reference Board Features Feature Description Form Factor Full-length PCI-X card (312mm x 107mm) ® ™ Integrated Intel XScale core Processor 500 MHz and 800Mhz core frequencies supported...

  • Page 139: Jtag Circuitry For Debug

    Intel® 80331 I/O Processor Design Guide JTAG Circuitry for Debug JTAG Circuitry for Debug ® Certain restrictions exist in order to use JTAG based debuggers with the Intel XScale microarchitecture. This is primarily due to the Tap Controller reset requirements of the Intel ® XScale microarchitecture and the reset requirements of specific JTAG debuggers.

  • Page 140: Jtag Signals / Header

    Intel® 80331 I/O Processor Design Guide JTAG Circuitry for Debug 11.2 JTAG Signals / Header Figure 71 is the pin definition (20-pin standard ARM connector) for JTAG. Figure 71. JTAG Header Pin Out VTref Vsupply nTRST RTCK nSRST DBGRQ DGBACK...

  • Page 141: System Requirements

    Intel® 80331 I/O Processor Design Guide JTAG Circuitry for Debug 11.3 System Requirements In order to successfully invoke a debug session, the JTAG debug unit must be able to control nTRST and nSRST independently. The nTRST signal allows the debugger to get the TAP controller in a known state.

  • Page 142: Jtag Hardware Requirements

    11.4 JTAG Hardware Requirements ® Due to the conflicting requirements of Multi-ICE* and the Intel XScale microarchitecture, it is necessary to incorporate a circuit that can drive TRST# low at power up and weakly pull it high at all other times. The following section details the circuits required for the Macraigor Raven*, WindRiver Systems* visionPROBE* / visionICE*, and ARM* Multi-ICE*.

  • Page 143: Debug Connectors And Logic Analyzer Connectivity

    Intel® 80331 I/O Processor Design Guide Debug Connectors and Logic Analyzer Connectivity Debug Connectors and Logic Analyzer Connectivity 12.1 Probing PCI-X Signals To ease the probing and debug of the PCI-X signals it is recommended to passively probe the PCI-X bus signals with a logic analyzer. This can be accomplished by placing six AMP...

  • Page 144: Logic Analyzer Pod 3

    Intel® 80331 I/O Processor Design Guide Debug Connectors and Logic Analyzer Connectivity Table 79. Logic Analyzer Pod 2 Mictor-38 #1 Pin Number Odd Pod Logic Analyzer Channel Number PCI-X Signal Name CLK/16 FRAME DEVSEL TRDY C/BE2 C/BE3 IDSEL INTD INTC...

  • Page 145: Logic Analyzer Pod 5

    Intel® 80331 I/O Processor Design Guide Debug Connectors and Logic Analyzer Connectivity Table 81. Logic Analyzer Pod 4 Mictor-38 # 2 Pin Number Odd Pod Logic Analyzer Channel Number PCI-X Signal Name CLK/16 UNUSED AD31 AD30 AD29 AD28 AD27 AD26...

  • Page 146: Logic Analyzer Pod 6

    Intel® 80331 I/O Processor Design Guide Debug Connectors and Logic Analyzer Connectivity Table 83. Logic Analyzer Pod 6 Mictor-38 Pin Number Even Pod Logic Analyzer Channel Number PCI-X Signal Name CLK/16 Unused AD63 AD62 AD60 AD59 AD58 AD57 AD56 AD55...

  • Page 147: References

    PCI Special Interest Group “Terminating Differential Signals on PCBs” , Steve Kaufer, Kelee Crisafulli, Printed Circuit Design, March 1999 Intel documentation is available from your local Intel Sales Representative or Intel Literature Sales. To obtain Intel literature write to or call:...

  • Page 148: Electronic Information

    Intel® 80331 I/O Processor Design Guide References 13.2 Electronic Information Table 86. Electronic Information The Intel World-Wide Web (WWW) Location: http://www.intel.com Customer Support (US and Canada): 800-628-8686...

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