Intel 82496 CACHE CONTROLLER User Manual page 291

HARDWARE INTERFACE
5.2.2.104. MWB/WT#
MWB!WT# Memory Write-BacklWrite-Through
Forces write-back or write-through policy.
Input to 82496 Cache Controller (pin lO4)
Synchronous to ClK
Signal Description
MWBJWT# is a 82496 Cache Controller input that is sampled at the closing of the snoop
window (at SWEND# activation). If sampled low, the current line fill is placed in the 82496
Cache Controller in the [S] (write-through) state.
MWB/WT# is used in many situations. For example, when a cache-to-cache transfer updates
memory and leaves valid data in another cache (i.e., does not assert SNPINV), the line must be
put in the [S] state. Also, a portion of memory may be designated as write-through by making
MWBJWT#=O for appropriate addresses.
DRCTM# does not affect the 82496 Cache. Controller if MWBJWT# is sampled low, or if
MRO# has been sampled active during KWEND#. If PWT is active or MRO# is sampled
active, the line is placed in the [S] state regardless of MWBJWT#.
When Sampled
MWB/WT# is sampled on the first CLK edge on which SWEND# is sampled active.
MWBJWT# is sampled during SWEND# of linefills, allocations, and write-throughs with
potential upgrade (e.g. a write hit to S state which is not read-only and PWT is inactive). If
MWBJWT# is not being sampled, it need not meet set-up and hold times.
Relation to Other Signals
Pin Symbol Relation to Other Signals
DRCTM# If MWB!WT# is sampled low during SWEND#, DRCTM# is ignored.
SWEND# Both MWBIWT# and DRCTM# are sampled with SWEND# assertion.
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