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82491 CACHE SRAM
Intel 82491 CACHE SRAM Manuals
Manuals and User Guides for Intel 82491 CACHE SRAM. We have
1
Intel 82491 CACHE SRAM manual available for free PDF download: User Manual
Intel 82491 CACHE SRAM User Manual (480 pages)
Volume 2: 82496 Cache Controller and 82491 Cache SRAM data book
Brand:
Intel
| Category:
Computer Hardware
| Size: 23.84 MB
Table of Contents
Table of Contents
8
Table of Contents
17
Table Title Page
18
Chapter 1 Pinouts
22
Pentium™ Processor Pinouts
22
Pinout Diagrams
22
82496 Cache Controller Pinouts
24
82491 Cache SRAM Memory Pinouts
26
Mooe
27
Pentium Processor
28
Pentium™ Processor Pin Cross Reference by Pin Name
28
Pentium™ Processor/Mbc Interface Signals
28
Pin Cross Reference Tables
28
82496 Cache Controller
30
82491 Cache SRAM
33
BRIEF PIN Descriptions
33
Meoc
33
Mfrz
33
Mhitm
36
Mistb
36
Mken
36
Moclk
36
Mro
36
Msel
36
Mthit
36
Mwb/Wt
36
Pentium™ Processor/82496 Cache Controller Interface Signals
36
Pentium™ Processor/82491 Cache SRAM Interface Signals
36
Pentium™ Processor CPU-Cache Chip Set Brief Pin Descriptions
37
Mx4/8
50
Mzbt
52
Pentium™ Processor CPU-Cache Chip Set Internal Pull-Up Resistors
57
Pentium™ Processor CPU-Cache Chip Set Glitch Free Pins
57
Pentium™ Processor CPU-Cache Chip Set Internal Pull-Down Resistors
57
Signal Interconnects on Optimized Interface
59
Pin States During RESET
60
Pentium™ Processor CPU-Cache Chip Set Output Pins
61
Nene
63
Pentium™ Processor CPU-Cache Chip Set Input Pins
64
Nmi
66
Par
66
Snpinv
66
Snpnca
66
Snpstb
66
Sweno
66
Sync
66
Tck
66
Tms
66
Toi
66
Trst
67
W/R
67
Way
67
Wb/Wt
67
Pentium™ Processor CPU-Cache Chip Set Input/Output Pins
68
Chapter 2 Cache Architecture Overview
70
82496 Cache Controller
73
Cpu/Cache Core Description
73
Main Features
73
82491 Cache Srams
74
Memory Bus Controller
75
Configuration
76
Physical Cache
76
Clocked (Asynchronous) Snoop Mode
77
Memory Bus Modes
77
Snoop Modes
77
Strobed Snoop Mode
77
Synchronous Snoop Mode
77
Clocked Memory Bus Mode
78
Pentium Processor Bus Interface
78
Strobed Memory Bus Mode
78
82496 Cache Controller/82491 Cache Sram Optimized Interface
79
Memory Bus Interface
79
Snooping Logic
79
Pentium™ Processor Signals Latched in the 82496 Cache Controller and 82491 Cache SRAM
79
Cycle Control Logic
80
Test
80
Chapter 3 Component Operation
82
82496 Cache Controller Cache Consistency Protocol
84
Write-Back Cache Designs
84
WRITE-THROUGH CACHE Designs
84
Mesi Cache Consistency Protocol Model
85
BASIC MESI STATE Transitions
86
Basic MESI State Transitions
87
MESI State Changes Resulting from CPU Bus Operations
88
Read Hit
88
Read Miss
88
Write Hit
89
WRITE Miss
89
Write Miss with Allocation
89
MESI State Changes Resulting from Memory Bus Masters
90
Snooping
90
CACHE Synchronization
91
Cacheability Attributes: PCD, MKEN
91
Mesi State Changes Following Cycles with Special Attributes
91
Write through Protocol: PWT, MWB/WT
91
Locked Accesses: LOCK
92
Read Only Accesses: MRO
92
CPU Bus Signals
93
Direct-To-Modified Attribute: DRCTM
93
State Transitions
93
Memory Bus Signals
94
Cycles Resulting from State Transitions
95
Tag State
95
Tag State and Cycles.resulting from State Transitions
95
MESI State Tables (82496 Cache Controller State Changes)
97
Master 82496 Cache Controller Read Cycle
97
Master 82496 Cache Controller Write Cycle
98
Snooping 82496 Cache Controller with Invalidation Request
99
Snooping 82496 Cache Controller Without Invalidation Request
99
SYNC Cycles
99
Inclusion
100
FLUSH Cycles
100
PRIMARY to SECONDARY CACHE Coherency
100
Inquire and Back-Invalidation Cycles
101
MESI State Tables (Pentium Processor CPU-Cache Chip Set State Changes)
102
Write Once Policy
102
MESI State Changes for READ Cycles: CPU to 82496 Cache Controller
103
82491 Cache SRAM Caches
103
MESI State Changes for WRITE Cycles: CPU to 82496 Cache Controller
104
82491 Cache SRAM Caches
104
Chapter 4 Cache Initialization and Configuration
108
Configuration Signal Sampling During Reset
111
Initialization Required for Chip Set Mode
112
Memory Bus Width
113
Physical Cache
113
Line Ratio
114
Tagram Size
114
Tagram Structure
114
Lines Per Sector (LIS)
115
Cache Size
116
Configurable Address Connections
116
82491 Cache SRAM Bus Configuration
117
4.2.10. CPU to 82491 Cache SRAM Address Configurations
118
82491 Cache SRAM Parity Configuration
118
4.2.11. Bus Driver Buffer Selection
119
Cache Modes
119
Memory Bus Modes
119
Clocked Mode
120
Configuration of Memory Bus Mode
120
Snoop Modes
120
Strobed Mode
120
Configuration of Snoop Mode
121
Description
121
Strong/Weak Write Ordering
121
Configuration
122
HARDWARE INTERFACE Page
124
MEMORY BUS CONTROLLER Considerations
126
Cycle Control
127
IDENTIFYING and EXECUTING Cycles
129
Cacheable Read Miss
131
Read Hit
131
Non-Cacheable Read Miss
132
Write Hit Lsi
132
Write Hit [EJ, [M]
132
Write Miss: no Allocation, Allocation
132
Locked
133
Replacement
133
Snoop Write Back
133
Cache-To-Cache Transfer
134
Read for Ownership
134
1/0 Cycles
135
FLUSH and SYNC Cycles
135
Special Cycles
135
Choosing a Snooping Mode
136
Snooping
136
Synchronous Snooping Mode
136
Asynchronous Snooping Mode
137
Strobed Snooping Mode
138
Snoop Operation
139
Snoop Blocking
142
When Snooping Is Not Allowed
144
SNOOPING DURING LOCKED Cycles
145
SNOOP WRITE BACK Cycles
146
Snooping During Split Locked Cycles
146
Address Integrity
147
Cpu Bus Address Parity
147
Memory Bus Address Parity
147
Data Control
148
Cpu Data Bus Transfer Control
149
Memory Bus Mode Selection
149
82491 Cache SRAM Intelligent Dual-Ported Cache Memory
150
82491 Cachesramdatapath
150
Memory Cycle Buffers
151
Write-Back and Snoop Buffers
151
MEMORY BUS CONTROL Signals
152
82491 CACHE SRAM PARITY Devices
153
Signal Synchronization
154
Handling of Large Caches I Larger Line Sizes
155
Warm Reset
155
5.1.10. 82496 Cache Controller Guaranteed Signal Relationships
156
5.1.11. 82496 Cache Controller Cycle Progress Requirements
157
82496 Cache Controller and 82491 Cache SRAM CRDY# Requirements
157
82496 Cache Controller Input Signal Recognition Requirements
157
82496 Cache Controller Cycle Attribute Sampling Requirements
158
Pentium Processor, 82496 Cache Controller, and 82491 Cache SRAM BRDY# Requirements
158
82496 Cache Controller Cycle Progress Signal Sampling Requirements
159
5.1.17. 82491 Cache SRAM Data Control Signal Requirements
160
5.1.18. Semaphore (Strong Write Ordering) Consistency
160
CONFIGURATION Signals
161
CYCLE ATTRIBUTE / PROGRESS Signals
161
Cycle Control Signals
161
Detailed Pentium Processor Cpu-Cache Chip Set Pin Descriptions
161
Signal/Category Cross-Reference
161
SNOOPING Signals
161
82496 Cache Controller/82491 Cache Sram Optimized Interface Signals
162
Cache Synchronization Signals
162
CPU Signals
162
Memory Address Bus and Address Control Signals
162
Memory Data Bus and Data Control Signals
162
PENTIUM PROCESSOR BUS OPTIMIZED INTERFACE Signals
162
Test Signals
162
Pentium Processor CPU-Cache Chip Set Detailed Pin Descriptions
163
A20M
164
Ads
165
Adsc
166
Ahold
167
Apchk
169
Aperr
170
Apic
171
Be#,Be[7:0]
172
Bgt
173
Blast
175
Ble
176
Blec
177
Boff
179
Bp[3:2], Pm/Bp[1 :0]
180
Brdy
181
Brdyc
183
Brdyc1
184
Brdyc2
185
Breq
186
Bt[3:0]
187
Bus
188
Buschk
189
Cache
190
Cads
191
Cahold
193
Ccache
194
CD/C
195
Cdata[7:0]
196
Cdts
197
Cfa[6:0],Set[1 0:0],Tag[11 :0]
199
Cfg[2:0]
200
Cldrv
201
Clk
202
CM/Io
203
Cna
204
Cpcd
205
Cpwt
206
Crdy
207
Cscyc
209
Cw/R
210
Cway
211
D/C
212
D[63:0]
213
Dp[7:0]
214
Drctm
215
Eads
217
Ewbe
218
Ferr
219
Flush
220
Frcmc
222
Fsiout
223
Highz
225
Hit
226
Hitm
227
Hlda
228
Hold
229
Ibt
230
Ierr
231
Ignne
232
Init
233
Intr
234
Inv
235
Iperr
236
Ken
239
Klock
241
Kwend
243
Lock
245
Lr[1 :0]
246
M/Io
247
Maldrv
248
Male
249
Maoe
250
Map
252
Maperr
253
Mawea
254
Mbale
255
Mbaoe
256
Mbe
258
Mbrdy
260
Mbt[3:0]
262
Mcache
264
Mcfa[6:0]. Mset[10:0]. Mtag[11 :0]
266
Mclk
268
Mcyc
269
Mdata[7:0]
270
Mdldrv
272
Wba
339
Wbtyp
340
Wbwe
341
Wrarr
342
Wwor
343
Chapter 6 Memory Bus Functional Description
344
READ Cycles
346
Read Hit Cycles
346
Read Miss Cycles
349
With Clean Replacement
349
With Replacement of Modified Line
352
Non Cacheable Read Miss Cycles
354
WRITE Cycles
355
Write Miss with Allocation Cycles
359
Locked Read-Modify-Write Cycles
361
Chapter 7 Electrical Specifications
370
Connection Specifications
370
Decoupling Recommendations
370
Maximum Ratings
370
Power and Ground
370
Specifications
371
Optimized Interface
373
Specifications
373
Flight Time Specification
374
Signal Quality
374
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