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CONTENTS CHAPTER 1 INTRODUCTION HOW TO USE THIS MANUAL..................1-2 RELATED DOCUMENTS ....................1-3 ELECTRONIC SUPPORT SYSTEMS ................1-4 1.3.1 FaxBack Service ...................... 1-4 1.3.2 Bulletin Board System (BBS) ................... 1-5 184.108.40.206 How to Find Ap BUILDER Software and Hypertext Documents on the BBS .....................
CONTENTS INTERRUPTS AND EXCEPTION HANDLING ............2-39 2.3.1 Interrupt/Exception Processing ................2-39 220.127.116.11 Non-Maskable Interrupts ................2-42 18.104.22.168 Maskable Interrupts ..................2-43 22.214.171.124 Exceptions .....................2-43 2.3.2 Software Interrupts ....................2-45 2.3.3 Interrupt Latency .....................2-45 2.3.4 Interrupt Response Time ..................2-46 2.3.5 Interrupt and Exception Priority ................2-46 CHAPTER 3 BUS INTERFACE UNIT MULTIPLEXED ADDRESS AND DATA BUS ..............
CONTENTS CHAPTER 4 PERIPHERAL CONTROL BLOCK PERIPHERAL CONTROL REGISTERS................ 4-1 PCB RELOCATION REGISTER..................4-1 RESERVED LOCATIONS ..................... 4-4 ACCESSING THE PERIPHERAL CONTROL BLOCK ..........4-4 4.4.1 Bus Cycles .......................4-4 4.4.2 READY Signals and Wait States ................4-4 4.4.3 F-Bus Operation .......................4-5 126.96.36.199 Writing the PCB Relocation Register ...............4-6 188.8.131.52...
CONTENTS CHAPTER 6 CHIP-SELECT UNIT COMMON METHODS FOR GENERATING CHIP-SELECTS........6-1 CHIP-SELECT UNIT FEATURES AND BENEFITS ............6-1 CHIP-SELECT UNIT FUNCTIONAL OVERVIEW ............6-2 PROGRAMMING ......................6-6 6.4.1 Initialization Sequence ....................6-6 6.4.2 Programming the Active Ranges ................6-12 184.108.40.206 UCS Active Range ..................6-12 220.127.116.11 LCS Active Range ..................6-13 18.104.22.168...
CONTENTS 9.2.4 Pulsed and Variable Duty Cycle Output ..............9-14 9.2.5 Enabling/Disabling Counters ...................9-15 9.2.6 Timer Interrupts .......................9-16 9.2.7 Programming Considerations ..................9-16 TIMING ........................9-16 9.3.1 Input Setup and Hold Timings .................9-16 9.3.2 Synchronization and Maximum Frequency .............9-17 22.214.171.124 Timer/Counter Unit Application Examples .............9-17 9.3.3 Real-Time Clock .....................9-17 9.3.4...
CONTENTS 10.2.1.8 Setting the Relative Priority of a Channel ............10-19 10.2.2 Suspension of DMA Transfers ................10-20 10.2.3 Initializing the DMA Unit ..................10-20 10.3 HARDWARE CONSIDERATIONS AND THE DMA UNIT ......... 10-20 10.3.1 DRQ Pin Timing Requirements ................10-20 10.3.2 DMA Latency ......................10-21 10.3.3 DMA Transfer Rates .....................10-21 10.3.4...
CONTENTS A.2.3 Bit Manipulation Instructions ................... A-9 A.2.3.1 Shift Instructions ..................... A-9 A.2.3.2 Rotate Instructions ..................A-10 APPENDIX B INPUT SYNCHRONIZATION WHY SYNCHRONIZERS ARE REQUIRED ..............B-1 ASYNCHRONOUS PINS....................B-2 APPENDIX C INSTRUCTION SET DESCRIPTIONS APPENDIX D INSTRUCTION SET OPCODES AND CLOCK CYCLES INDEX...
CONTENTS FIGURES Figure Page Simplified Functional Block Diagram of the 80C186 Family CPU ........2-2 Physical Address Generation ..................2-3 General Registers ......................2-4 Segment Registers .......................2-6 Processor Status Word ....................2-9 Segment Locations in Physical Memory..............2-10 Currently Addressable Segments................2-11 Logical and Physical Address ..................2-12 Dynamic Code Relocation ..................2-14 2-10 Stack Operation......................2-16...
CONTENTS FIGURES Figure Page 3-15 Generating a Normally Not-Ready Bus Signal ............3-16 3-16 Generating a Normally Ready Bus Signal ..............3-17 3-17 Normally Not-Ready System Timing ................3-18 3-18 Normally Ready System Timings ................3-19 3-19 Typical Read Bus Cycle .....................3-21 3-20 Read-Only Device Interface ..................3-22 3-21 Typical Write Bus Cycle....................3-23 3-22...
CONTENTS FIGURES Figure Page UMCS Register Definition.....................6-7 LMCS Register Definition .....................6-8 MMCS Register Definition ....................6-9 PACS Register Definition ...................6-10 MPCS Register Definition...................6-11 6-10 MCS3:0 Active Ranges ....................6-14 6-11 Wait State and Ready Control Functions ..............6-16 6-12 Using Chip-Selects During HOLD ................6-18 6-13 Typical System ......................6-19 Refresh Control Unit Block Diagram................7-1...
CONTENTS TABLES Table Page Comparison of 80C186 Modular Core Family Products ..........1-2 Related Documents and Software................1-3 Implicit Use of General Registers .................2-5 Logical Address Sources....................2-13 Data Transfer Instructions ..................2-18 Arithmetic Instructions ....................2-20 Arithmetic Interpretation of 8-Bit Numbers ..............2-21 Bit Manipulation Instructions ..................2-21 String Instructions.......................2-22 String Instruction Register and Flag Use..............2-23 Program Transfer Instructions ..................2-25...
CONTENTS TABLES Table Page 11-6 80C187 Processor Control Instructions..............11-6 11-7 80C187 I/O Port Assignments ..................11-10 Instruction Format Variables..................C-1 Instruction Operands ....................C-2 Flag Bit Functions......................C-3 Instruction Set ......................C-4 Operand Variables ...................... D-1 Instruction Set Summary ..................... D-2 Machine Instruction Decoding Guide................
CONTENTS EXAMPLES Example Page Initializing the Power Management Unit for Idle or Powerdown Mode .......5-16 Initializing the Power Management Unit for Power-Save Mode .........5-22 Initializing the Chip-Select Unit...................6-20 Initializing the Refresh Control Unit ................7-11 Initializing the Interrupt Control Unit for Master Mode ..........8-31 Configuring a Real-Time Clock...................9-18 Configuring a Square-Wave Generator ..............9-21 Configuring a Digital One-Shot...................9-22...
As technology advanced and turned toward small geometry CMOS processes, it became clear that a new 80186 was needed. In 1987 Intel announced the second generation of the 80186 family: the 80C186/C188. The 80C186 family is pin compatible with the 80186 family, while adding an enhanced feature set.
INTRODUCTION The 80C186 Modular Core family is the direct result of ten years of Intel development. It offers the designer the peace of mind of a well-established architecture with the benefits of state-of-the- art technology. Table 1-1. Comparison of 80C186 Modular Core Family Products...
The following table lists documents and software that are useful in designing systems that incor- porate the 80C186 Modular Core Family. These documents are available through Intel Literature. In the U.S. and Canada, call 1-800-548-4725 to order. In Europe and other international locations, please contact your local Intel sales office or distributor.
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CHAPTER 2 OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE The 80C186 Modular Microprocessor Core shares a common base architecture with the 8086, 8088, 80186, 80188, 80286, Intel386™ and Intel486™ processors. The 80C186 Modular Core maintains full object-code compatibility with the 8086/8088 family of 16-bit microprocessors, while adding hardware and software performance enhancements.
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Address Bus (20 Bits) General Σ Registers Data (16 Bits) ALU Data Bus Internal Communications (16 Bits) Registers Temporary Registers External Control Logic Instruction Queue Control 1 2 3 4 5 6 System Q Bus Flags (8 Bits) Execution Unit...
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE The Execution Unit does not connect directly to the system bus. It obtains instructions from a queue maintained by the Bus Interface Unit. When an instruction requires access to memory or a peripheral device, the Execution Unit requests the Bus Interface Unit to read and write data. Ad- dresses manipulated by the Execution Unit are 16 bits wide.
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE During periods when the Execution Unit is busy executing instructions, the Bus Interface Unit sequentially prefetches instructions from memory. As long as the prefetch queue is partially full, the Execution Unit fetches instructions. 2.1.3 General Registers The 80C186 Modular Core family CPU has eight 16-bit general registers (see Figure 2-3).
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE The data registers can be addressed by their upper or lower halves. Each data register can be used interchangeably as a 16-bit register or two 8-bit registers. The pointer registers are always access- ed as 16-bit values. The CPU can use data registers without constraint in most arithmetic and log- ic operations.
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Code Segment Data Segment Stack Segment Extra Segment Figure 2-4. Segment Registers 2.1.5 Instruction Pointer The Bus Interface Unit updates the 16-bit Instruction Pointer (IP) register so it contains the offset of the next instruction to be fetched. Programs do not have direct access to the Instruction Pointer, but it can change, be saved or be restored as a result of program execution.
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE 2.1.6 Flags The 80C186 Modular Core family has six status flags (see Figure 2-5) that the Execution Unit posts as the result of arithmetic or logical operations. Program branch instructions allow a pro- gram to alter its execution depending on conditions flagged by a prior operation. Different in- structions affect the status flags differently, generally reflecting the following states: •...
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE 2.1.7 Memory Segmentation Programs for the 80C186 Modular Core family view the 1 Mbyte memory space as a group of user-defined segments. A segment is a logical unit of memory that can be up to 64 Kbytes long. Each segment is composed of contiguous memory locations.
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Fully Overlapped Partly Segment D Disjoint Overlapped Logical Contiguous Segment C Segments Segment E Segment A Segment B Physical Memory 10000H 20000H 30000H A1036-0A Figure 2-6. Segment Locations in Physical Memory The four segment registers point to four “currently addressable” segments (see Figure 2-7). The currently addressable segments provide a work space consisting of 64 Kbytes for code, a 64 Kbytes for stack and 128 Kbytes for data storage.
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE FFFFFH Data: Code: Stack: Extra: A1037-0A Figure 2-7. Currently Addressable Segments The segment register is automatically selected according to the rules in Table 2-2. All information in one segment type generally shares the same logical attributes (e.g., code or data). This leads to programs that are shorter, faster and better structured.
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE 2C4H Physical 2C3H Address 2C2H Offset (3H) 2C1H Segment 2C0H Base 2BFH 2BEH 2BDH 2BCH 2BBH Offset Logical 2BAH (13H) Addresses 2B9H 2B8H 2B7H 2B6H 2B5H 2B4H 2B3H 2B2H 2B1H Segment 2B0H Base A1038-0A Figure 2-8.
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Table 2-2. Logical Address Sources Default Alternate Type of Memory Reference Offset Segment Base Segment Base Instruction Fetch NONE Stack Operation NONE Variable (except following) CS, ES, SS Effective Address String Source CS, ES, SS String Destination NONE BP Used as Base Register...
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Before After Relocation Relocation Code Segment Stack Segment Code Segment Data Stack Segment Segment Data Segment Extra Extra Segment Segment Free Space A1039-0A Figure 2-9. Dynamic Code Relocation To be dynamically relocatable, a program must not load or alter its segment registers and must not transfer directly to a location outside the current code segment.
0FFFF0H. • Locations 0F8H through 0FFH in I/O space are reserved for communication with other Intel hardware products and must not be used. On the 80C186 core, these addresses are used as I/O ports for the 80C187 numerics processor extension.
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE POP AX POP BX PUSH AX Existing Stack 1062 1062 1062 1060 1060 1060 105E 105E 105E 105B 105B 105B 105A 105A 105A 1058 1058 1058 1056 1056 1056 1054 1054 1054 1052 1052 1052 1050 1050...
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE SOFTWARE OVERVIEW All 80C186 Modular Core family members execute the same instructions. This includes all the 8086/8088 instructions plus several additions and enhancements (see Appendix A, “80C186 In- struction Set Additions and Extensions”). The following sections describe the instructions by cat- egory and provide a detailed discussion of the operand addressing modes.
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE 126.96.36.199 Data Transfer Instructions The instruction set contains 14 data transfer instructions. These instructions move single bytes and words between memory and registers. They also move single bytes and words between the AL or AX register and I/O ports. Table 2-3 lists the four types of data transfer instructions and their functions.
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE LAHF Z U A U P U C SAHF 6 5 4 3 2 1 0 PUSHF POPF U = Undefined; Value is indeterminate O = Overflow Flag D = Direction Flag I = Interrupt Enable Flag T = Trap Flag S = Sign Flag Z = Zero Flag...
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Table 2-5 shows the interpretations of various bit patterns according to number type. Binary num- bers can be 8 or 16 bits long. Decimal numbers are stored in bytes, two digits per byte for packed decimal and one digit per byte for unpacked decimal.
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Individual bits in bytes and words can also be rotated. The processor does not discard the bits ro- tated out of an operand. The bits circle back to the other end of the operand. The number of bits to be rotated is taken from the count operand, which can specify either an immediate value or the CL register.
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE String instructions automatically update the SI register, the DI register, or both, before processing the next string element. The Direction Flag (DF) determines whether the index registers are auto- incremented (DF = 0) or auto-decremented (DF = 1). The processor adjusts the DI, SI, or both registers by one for byte strings or by two for word strings.
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Unconditional transfer instructions can transfer control either to a target instruction within the current code segment (intrasegment transfer) or to a different code segment (intersegment trans- fer). The assembler terms an intrasegment transfer SHORT or NEAR and an intersegment trans- fer FAR.
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Table 2-9. Program Transfer Instructions Conditional Transfers JA/JNBE Jump if above/not below nor equal JAE/JNB Jump if above or equal/not below JB/JNAE Jump if below/not above nor equal JBE/JNA Jump if below or equal/not above Jump if carry JE/JZ Jump if equal/zero...
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Iteration control instructions can be used to regulate the repetition of software loops. These in- structions use the CX register as a counter. Like the conditional transfers, the iteration control in- structions are self-relative and can transfer only to targets that are within –128 to +127 bytes of themselves.
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE 188.8.131.52 Processor Control Instructions Processor control instructions (see Table 2-11) allow programs to control various CPU functions. Seven of these instructions update flags, four of them are used to synchronize the microprocessor with external events, and the remaining instruction causes the CPU to do nothing. Except for flag operations, processor control instructions do not affect the flags.
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Immediate operands are constant data contained in an instruction. Immediate data can be either 8 or 16 bits in length. Immediate operands are available directly from the instruction queue and can be accessed quickly. As with a register operand, no bus cycles need to be run to get an imme- diate operand.
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Single Index Double Index Encoded in the Instruction Explicit Effective in the Displacement Address Instruction 0000 0000 Assumed Unless Overridden by Prefix 0000 0000 Physical Addr A1015-0A Figure 2-12. Memory Address Computation The displacement is an 8- or 16-bit number contained in the instruction. The displacement gen- erally is derived from the position of the operand’s name (a variable or label) in the program.
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE The BX or BP register can be specified as the base register for an effective address calculation. Similarly, either the SI or the DI register can be specified as the index register. The displacement value is a constant.
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Opcode Mod R/M A1017-0A Figure 2-14. Register Indirect Addressing Opcode Mod R/M Displacement A1018-0A Figure 2-15. Based Addressing Based addressing provides a simple way to address data structures that may be located in different places in memory (see Figure 2-16).
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE High Address Displacement Displacement (Rate) Status (Rate) Rate Sick Base Base Register Register Dept Employee Status Rate Sick Dept Employee Low Address A1019-0A Figure 2-16. Accessing a Structure with Based Addressing With indexed addressing, the effective address is calculated by summing a displacement and the contents of an index register (SI or DI, see Figure 2-17).
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Opcode Mod R/M Displacement A1020-0A Figure 2-17. Indexed Addressing High Address Array (8) Displacement Array (7) Displacement Array (6) Array (5) Index Register Index Register Array (4) Array (3) Array (2) Array (1) Array (0) 1 Word Low Address A1021-0A...
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Based index addressing generates an effective address that is the sum of a base register, an index register and a displacement (see Figure 2-19). The two address components can be determined at execution time, making this a very flexible addressing mode. Opcode Mod R/M Displacement...
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE High Address Displacement Parm 2 Displacement Parm 1 Old BP Base Register (BP) Base Register (BP) Old BX Old AX Array (6) Index Register Index Register Array (5) Array (4) Array (3) Array (2) Array (1) Array (0) Count...
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Opcode Source EA Destination EA A1025-0A Figure 2-21. String Operand 184.108.40.206 I/O Port Addressing Any memory operand addressing modes can be used to access an I/O port if the port is memory- mapped. String instructions can also be used to transfer data to memory-mapped ports with an appropriate hardware interface.
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE 220.127.116.11 Data Types Used in the 80C186 Modular Core Family The 80C186 Modular Core family supports the data types described in Table 2-12 and illustrated in Figure 2-23. In general, individual data elements must fit within defined segment limits. Table 2-12.
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Signed Byte Unsigned Byte Sign Bit Magnitude Magnitude 15 14 Unsigned Signed Word Word Sign Bit Magnitude Magnitude Signed Double Word* Sign Bit Magnitude Signed Quad Word* Sign Bit Magnitude Binary Coded Decimal (BCD) BCD Digit n BCD Digit 1 BCD Digit 0...
Each interrupt or exception is given a type number, 0 through 255, corresponding to its position in the Interrupt Vector Table. Note that in- terrupt types 0–31 are reserved for Intel and should not be used by an application program. 2-39...
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Memory Table Vector Memory Table Vector Address Entry Definition Address Entry Definition Type 255 Type 11 - DMA1 User Type 10 - DMA0 Available Type 32 Type 9 - Reserved Type 31 Type 8 - Timer 0 Reserved Type 7 - ESC Opcode Type 20...
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE The Trap Flag bit and Interrupt Enable bit are cleared in the Processor Status Word. This prevents maskable interrupts or single step exceptions from interrupting the processor during the interrupt service routine. The current CS and IP are pushed onto the stack. The CPU fetches the new CS and IP for the interrupt vector routine from the Interrupt Vector Table and begins executing from that point.
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Interrupt Enable Bit Stack Trap Flag Processor Status Word Code Segment Register Instruction Pointer Interrupt Vector Table A1029-0A Figure 2-26. Interrupt Sequence 18.104.22.168 Non-Maskable Interrupts The Non-Maskable Interrupt (NMI) is the highest priority interrupt. It is usually reserved for a catastrophic event such as impending power failure.
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE 22.214.171.124 Maskable Interrupts Maskable interrupts are the most common way to service external hardware interrupts. Software can globally enable or disable maskable interrupts. This is done by setting or clearing the Inter- rupt Enable bit in the Processor Status Word. The Interrupt Control Unit processes the multiple sources of maskable interrupts and presents them to the core via a single maskable interrupt input.
80C188 Modular Core Family members do not support the 80C187 interface and always generate the Escape Opcode Fault. The 80C186EA will generate the Escape Opcode Fault regardless of the state of the Escape Trap bit unless it is in Numerics Mode.
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE 2.3.2 Software Interrupts A Software Interrupt is caused by executing an “INTn” instruction. The n parameter corresponds to the specific interrupt type to be executed. The interrupt type can be any number between 0 and 255.
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE 2.3.4 Interrupt Response Time Interrupt response time is the time from the CPU recognizing an interrupt until the first instruction in the service routine is executed. Interrupt response time is less for interrupts or exceptions which supply their own vector type.
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Only the single step exception can occur concurrently with another exception. At most, two ex- ceptions can occur at the same instruction boundary and one of those exceptions must be the sin- gle step. Single step is a special case; it is discussed on page 2-48. Ignoring single step (for now), only one exception can occur at any given instruction boundary.
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Single step priority is a special case. If an interrupt (NMI or maskable) occurs at the same instruc- tion boundary as a single step, the interrupt vector is taken first, then is followed immediately by the single step vector.
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Interrupt Enable Bit (IE) = 1 Trap Flag (TF) = 1 Divide Timer Interrupt Push PSW, CS, IP Interrupt Enable Bit (IE) = 0 Fetch Divide Error Vector Trap Flag (TF) = 0 Interrupt Enable Bit (IE) = 0 Push PSW, CS, IP Trap Flag (TF) = 0 Fetch NMI Vector...
CHAPTER 3 BUS INTERFACE UNIT The Bus Interface Unit (BIU) generates bus cycles that prefetch instructions from memory, pass data to and from the execution unit, and pass data to and from the integrated peripheral units. The BIU drives address, data, status and control information to define a bus cycle. The start of a bus cycle presents the address of a memory or I/O location and status information defining the type of bus cycle.
BUS INTERFACE UNIT Physical Implementation Physical Implementation of the Address Space for of the Address Space for 16-Bit Systems 8-Bit Systems 1 MByte 512 KBytes 512 KBytes FFFFF FFFFF FFFFE FFFFE FFFFD FFFFC A19:0 D7:0 A19:1 D15:8 D7:0 A1100-0A Figure 3-1. Physical Data Bus Models Byte transfers to even addresses transfer information over the lower half of the data bus (see Fig- ure 3-2).
BUS INTERFACE UNIT Even Byte Transfer Y + 1 X + 1 A19:1 D15:8 D7:0 (Low) (High) Odd Byte Transfer Y + 1 (X + 1) A19:1 D7:0 D15:8 (High) (Low) A1104-0A Figure 3-2. 16-Bit Data Bus Byte Transfers...
BUS INTERFACE UNIT (X + 1) A19:1 D15:8 D7:0 (Low) (Low) A1107-0A Figure 3-3. 16-Bit Data Bus Even Word Transfers During a byte read operation, the BIU floats the entire 16-bit data bus, even though the transfer occurs on only one half of the bus. This action simplifies the decoding requirements for read-only devices (e.g., ROM, EPROM, Flash).
BUS INTERFACE UNIT First Bus Cycle (X + 1) A19:1 D15:8 D7:0 (High) (Low) Second Bus Cycle Y + 1 X + 1 A19:1 D15:8 D7:0 (Low) (High) A1108-0A Figure 3-4. 16-Bit Data Bus Odd Word Transfers 3.2.2 8-Bit Data Bus The memory address space on an 8-bit data bus is physically implemented as one bank of 1 Mbyte (see Figure 3-1 on page 3-2).
BUS INTERFACE UNIT For word transfers, the word address defines the first byte transferred. The second byte transfer occurs from the word address plus one. Figure 3-5 illustrates a word transfer on an 8-bit bus in- terface. Second Bus Cycle First Bus Cycle (X + 1) A19:0...
BUS INTERFACE UNIT 3.3.1 16-Bit Bus Memory and I/O Requirements A 16-bit bus has certain assumptions that must be met to operate properly. Memory used to store instruction operands (i.e., the program) and immediate data must be 16 bits wide. Instruction prefetch bus cycles require that both banks be used.
BUS INTERFACE UNIT CLKOUT Valid Status S2:0 Data AD15:0 Address RD / WR A1507-0A Figure 3-6. Typical Bus Cycle Falling Rising CLKOUT Edge Edge Phase 1 Phase 2 (High Phase) (Low Phase) A1111-0A Figure 3-7. T-State Relation to CLKOUT Figure 3-8 shows the BIU state diagram. Typically a bus cycle consists of four consecutive T- states labeled T1, T2, T3 and T4.
BUS INTERFACE UNIT The address/status phase starts just before T1 and continues through T1. The data phase starts at T2 and continues through T4. Figure 3-9 illustrates the T-state relationship of the two phases. Bus Ready Request Pending HOLD Deasserted Halt Bus Cycle Bus Not Ready...
BUS INTERFACE UNIT or TI or TW or TI CLKOUT Address/ Data Phase Status Phase A1113-0A Figure 3-9. T-State and Bus Phases 3.4.1 Address/Status Phase Figure 3-10 shows signal timing relationships for the address/status phase of a bus cycle. A bus cycle begins with the transition of ALE and S2:0.
BUS INTERFACE UNIT or TI CLKOUT AD15:0 A19:16 Valid S2:0 Valid NOTES: : Clock high to ALE high, S2:0 valid. CHOV : Clock low to address valid, BHE valid. CLOV : Address valid to ALE low (address setup to ALE). AVLL : Clock high to ALE low.
BUS INTERFACE UNIT Latched Address Signals Signals From CPU A19:16 LA19:16 S2:0 LS2:0 AD15:8 LA15:8 AD7:0 LA7:0 A1102-0A Figure 3-11. Demultiplexing Address Information Table 3-1. Bus Cycle Types Status Bit Operation Interrupt Acknowledge I/O Read I/O Write Halt Instruction Prefetch Memory Read Memory Write Idle (passive)
BUS INTERFACE UNIT 3.4.2 Data Phase Figure 3-12 shows the timing relationships for the data phase of a bus cycle. The only bus cycle type that does not have a data phase is a bus halt. During the data phase, the bus transfers infor- mation between the internal units and the memory or peripheral device selected during the ad- dress/status phase.
BUS INTERFACE UNIT or TW or TI CLKOUT RD/ WR AD15:0 Valid Write Data Write Valid AD15:0 Read Data Read S2:0 NOTES: : Clock low to valid RD/ WR active; Write data valid CLOV : Clock low to status inactive CLOV : Data input valid to clock low CLIS...
BUS INTERFACE UNIT CLKOUT Valid S2:0 Address A19:16 Address Valid Write Data AD15:0 READY A1040-0A Figure 3-13. Typical Bus Cycle with Wait States ARDY BUS READY Rising Falling CLKOUT Edge Edge SRDY A1041-0A Figure 3-14. ARDY and SRDY Pin Block Diagram 3-15...
BUS INTERFACE UNIT A normally not-ready system is one in which ARDY and SRDY remain low at all times except to signal a ready condition. For any bus cycle, only the selected device drives either ready input high to complete the bus cycle. The circuit shown in Figure 3-15 illustrates a simple circuit to generate a normally not-ready signal.
BUS INTERFACE UNIT Wait State Module Enable READY Load CLKOUT Clock A1081-0A Figure 3-16. Generating a Normally Ready Bus Signal The ARDY input has two major timing concerns that can affect whether a normally ready or nor- mally not-ready signal may be required. Two latches capture the state of the ARDY input (see Figure 3-14 on page 3-15).
BUS INTERFACE UNIT or T3 or TW or TW CLKOUT ARDY SRDY In a Normally-Not-Ready system, wait states are inserted until (1 or 2) and 3 are met. 1. T CHIS : ARDY active to clock high (assumes ARDY remains active until 3). 2.
BUS INTERFACE UNIT CLKOUT ARDY In a Normally-Ready system, a wait state will be inserted when 1 & 2 are met. (Assumes SRDY is low.) : ARDY low to clock high CLIS : Clock high to ARDY high (ARDY inactive hold time) CLIH CLKOUT ARDY...
BUS INTERFACE UNIT An idle bus state may or may not drive the bus. An idle bus state following a bus read cycle con- tinues to float the bus. An idle bus state following a bus write cycle continues to drive the bus. The BIU drives no control strobes active in an idle state except to indicate the start of another bus cycle.
BUS INTERFACE UNIT and T define the maximum data access requirements for the memory device. These device parameters must be less than the value calculated in the equation column. An equal to or greater than result indicates that wait states must be inserted into the bus cycle. determines the maximum time the memory device can float its outputs before the next bus cycle begins.
BUS INTERFACE UNIT 126.96.36.199 Refresh Bus Cycles A refresh bus cycle operates similarly to a normal read bus cycle except for the following: • For a 16-bit data bus, address bit A0 and BHE drive to a 1 (high) and the data value on the bus is ignored.
BUS INTERFACE UNIT CLKOUT Status Valid S2:0 Address Valid A18:16 = 0, A19=Valid Status A19:16 Valid [A15:8] A15:0 Address Data Valid Valid [AD7:0] DT/R A1047-0A Figure 3-21. Typical Write Bus Cycle Table 3-4. Write Bus Cycle Types Status Bits Bus Cycle Type Write I/O —...
BUS INTERFACE UNIT Most memory and peripheral devices latch data on the rising edge of the write strobe. Address, chip-select and data must be valid (set up) prior to the rising edge of WR. T and T fine the minimum data setup requirements. The value calculated by their respective equations must be greater than the device requirements.
BUS INTERFACE UNIT The minimum device data hold time (from WR high) is defined by T . The calculated value must be greater than the minimum device requirements; however, the value can be changed only by decreasing the clock rate. Table 3-5.
BUS INTERFACE UNIT CLKOUT S2:0 INTA0 Note Note INTA1 AD15:0 Note [AD7:0] LOCK DT/R A19:16 A15:8 are unknown [A15:8] A19:16 are driven low RD, WR NOTE: Vector Type is read from AD7:0 only. INTA occurs during T2 in slave mode. A1048-0A Figure 3-23.
BUS INTERFACE UNIT Figure 3-24 shows a typical 82C59A interface example. Bus ready must be provided to terminate both bus cycles in the interrupt acknowledge sequence. NOTE Due to an internal condition, external ready is ignored if the device is configured in Cascade mode and the Peripheral Control Block (PCB) is located at 0000H in I/O space.
BUS INTERFACE UNIT 3.5.4 HALT Bus Cycle Suspending the CPU reduces device power consumption and potentially reduces interrupt latency time. The HLT instruction initiates two events: Suspends the Execution Unit. Instructs the BIU to execute a HALT bus cycle. The Idle or Powerdown power management mode (or the absence of both of them, known as Ac- tive Mode) affects the operation of the bus HALT cycle.
BUS INTERFACE UNIT After several TI bus states, all address/data, address/status and bus control pins drive to a known state when Powerdown or Idle Mode is enabled. The address/data and address/status bus pins force a low (0) state. Bus control pins force their inactive state. Figure 3-3 lists the state of each pin after entering the HALT bus state.
BUS INTERFACE UNIT CLKOUT S2:0 AD15:0 Note 1 Note 2 Note 3 [AD7:0] [A15:8] Note 2 Note 2 Note 3 A19:16 Note 4 [RFSH = 1] NOTES: 1. The AD15:0 [AD7:0] bus can be floating, driving a previous write data value, or driving the next instruction prefetch address value.
BUS INTERFACE UNIT 3.5.5 Temporarily Exiting the HALT Bus State A DMA request, refresh request or bus hold request causes the BIU to exit the HALT bus state temporarily. This can occur only when in the Active or Idle power management mode. The BIU returns to the HALT bus state after it completes the desired bus operation.
BUS INTERFACE UNIT CLKOUT S2:0 AD15:0 Addr [AD7:0] [A15:8] Address Note 1 A19:16 Note 1 Addr A19 = 1, A18:16 = 0 Note 2 Note 3 RFSH NOTES: 1. Previous bus cycle value. 2. Only occurs for BHE on the first refresh bus cycle after entering HALT. 3.
BUS INTERFACE UNIT T1 T2 T3 T4 T1 T2 T3 CLKOUT S2:0 Valid Status Valid Status AD15:0 Valid Data Addr Addr [AD7:0] [A15:8] Note Address Address A19:16 Addr Note Addr Note Valid Valid [RFSH=1] NOTE: Drives previous bus cycle value A1052-0A Figure 3-28.
BUS INTERFACE UNIT CLKOUT 8 1/2 clocks to first vector fetch S2:0 AD15:0 [AD7:0] [A15:8] Note [RFSH = 1] A19:16 Time is determined by PDTMR (4 1/2 clocks min.) NOTE: Previous bus cycle address value. A1054-0A Figure 3-29. Exiting HALT (Powerdown Mode) 3-34...
BUS INTERFACE UNIT 3.6.1 Buffering the Data Bus The BIU generates two control signals, DEN and DT/R, to control bidirectional buffers or trans- ceivers. The timing relationship of DEN and DT/R is shown in Figure 3-31. The following con- ditions require transceivers: •...
BUS INTERFACE UNIT A19:16 Latch Address Bus Processor AD15:0 Address Memory Transceiver Data Data Bus Device DT/ R CPU Local Bus Buffered Bus A1095-0A Figure 3-32. Buffered AD Bus System In a fully buffered system, DEN directly drives the transceiver output enable. A partially buffered system requires that DEN be qualified with another signal to prevent the transceiver from going active for local bus accesses.
BUS INTERFACE UNIT AD15:8 D15:8 MCS0 Buffer Buffered Data AD7:0 D7:0 DT/R Buffer Local Data A1058-0B Figure 3-33. Qualifying DEN with Chip-Selects 3.6.2 Synchronizing Software and Hardware Events The execution sequence of a program and hardware events occurring within a system are often asynchronous to each other.
BUS INTERFACE UNIT The WAIT instruction suspends program execution until one of two events occurs: an interrupt is generated, or the TEST input pin is sampled low. Unlike interrupts, the TEST input pin does not require that program execution be transferred to a new location (i.e., an interrupt routine is not executed).
BUS INTERFACE UNIT In general, prefix bytes (such as LOCK) are considered extensions of the instructions they pre- cede. Interrupts, DMA requests and refresh requests that occur during execution of the prefix are not acknowledged until the instruction following the prefix completes (except for instructions that are servicing interrupts during their execution, such as HALT, WAIT and repeated string primitives).Note that multiple prefix bytes can precede an instruction.
BUS INTERFACE UNIT CLKOUT QS0, QS1 A1059-0A Figure 3-34. Queue Status Timing MULTI-MASTER BUS SYSTEM DESIGNS The BIU supports protocols for transferring control of the local bus between itself and other de- vices capable of acting as bus masters. To support such a protocol, the BIU uses a hold request input (HOLD) and a hold acknowledge output (HLDA) as bus transfer handshake signals.
BUS INTERFACE UNIT CLKOUT HOLD HLDA AD15:0 Float A19:16 RD,WR Float DT/R S2:0,BHE LOCK NOTES: : HOLD input to clock low CLIS : Clock high to output float CHOF : Clock low to output float CLOF : Clock low to HLDA high CLOV A1097-0A Figure 3-35.
BUS INTERFACE UNIT The major factors that influence bus latency are listed below (in order from longest delay to short- est delay). Bus Not Ready — As long as the bus remains not ready, a bus hold request cannot be serviced.
BUS INTERFACE UNIT CLKOUT HOLD HLDA AD15:0 A19:16 RD, WR, BHE, S2:0 DT/R, LOCK NOTES: 1. HLDA is deasserted, signaling need to run refresh bus cycle. 2. External bus master terminates use of the bus. 3. HOLD deasserted. 4. Hold may be reasserted after one clock. 5.
BUS INTERFACE UNIT Latched HLDA HLDA RESOUT HOLD A1062-0A Figure 3-37. Latching HLDA The removal of HOLD must be detected for at least one clock cycle to allow the BIU to regain the bus and execute a refresh bus cycle. Should HOLD go active before the refresh bus cycle is complete, the BIU will release the bus and generate HLDA.
BUS INTERFACE UNIT CLKOUT HOLD HLDA AD15:0 RD, WR, BHE, DT / R, S2:0, A19:16 NOTES: : HOLD recognition setup to clock low CLIS : HOLD internally synchronized : Clock low to HLDA low CLOV : Clock high to signal active (high or low) CHOV : Clock low to signal active (high or low) CLOV...
BUS INTERFACE UNIT Internal error (e.g., divide error, overflow) interrupt vectoring sequence. Hardware (e.g., INT0, DMA) interrupt vectoring sequence. 80C187 Math Coprocessor error interrupt vectoring sequence. DMA bus cycles. 10. General instruction execution. This category includes read/write operations following a pipelined effective address calculation, vectoring sequences for software interrupts and numerics code execution.
CHAPTER 4 PERIPHERAL CONTROL BLOCK All integrated peripherals in the 80C186 Modular Core family are controlled by sets of registers within an integrated Peripheral Control Block (PCB). The peripheral control registers are physi- cally located in the peripheral devices they control, but they are addressed as a single block of registers.
Upper Bits ignored when the PCB is mapped to I/O space. NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 4-1. PCB Relocation Register...
PERIPHERAL CONTROL BLOCK Table 4-1. Peripheral Control Block Function Function Function Function Offset Offset Offset Offset Reserved Reserved Reserved D0SRCL Reserved Reserved Reserved D0SRCH Reserved Reserved Reserved D0DSTL Reserved Reserved Reserved D0DSTH Reserved Reserved Reserved D0TC Reserved Reserved Reserved D0CON Reserved Reserved Reserved...
PERIPHERAL CONTROL BLOCK RESERVED LOCATIONS Many locations within the Peripheral Control Block are not assigned to any peripheral. Unused locations are reserved. Reading from these locations yields an undefined result. If reserved reg- isters are written (for example, during a block MOV instruction) they must be set to 0H. NOTE Failure to follow this guideline could result in incompatibilities with future 80C186 Modular Core family products.
PERIPHERAL CONTROL BLOCK 4.4.3 F-Bus Operation The F-Bus functions differently than the external data bus for byte and word accesses. All write transfers on the F-Bus occur as words, regardless of how they are encoded. For example, the in- struction OUT DX, AL (DX is even) will write the entire AX register to the Peripheral Control Block register at location [DX].
PERIPHERAL CONTROL BLOCK 188.8.131.52 Writing the PCB Relocation Register Whenever mapping the Peripheral Control Block to another location, the user should program the Relocation Register with a byte write (i.e., OUT DX, AL). Internally, the Relocation Register is written with 16 bits of the AX register, while externally the Bus Interface Unit runs a single 8-bit bus cycle.
PERIPHERAL CONTROL BLOCK As an example, to relocate the Peripheral Control Block to the memory range 10000-100FFH, the user would program the PCB Relocation Register with the value 1100H. Since the Relocation Register is part of the Peripheral Control Block, it relocates to word 10000H plus its fixed offset. NOTE Due to an internal condition, external ready is ignored if the device is configured in Cascade mode and the Peripheral Control Block (PCB) is...
CHAPTER 5 CLOCK GENERATION AND POWER MANAGEMENT The clock generation and distribution circuits provide uniform clock signals for the Execution Unit, the Bus Interface Unit and all integrated peripherals. The 80C186 Modular Core Family processors have additional logic that controls the clock signals to provide power management functions.
CLOCK GENERATION AND POWER MANAGEMENT 184.108.40.206 Oscillator Operation A phase shift oscillator operates through positive feedback, where a non-inverted, amplified ver- sion of the input connects back to the input. A 360° phase shift around the loop will sustain the feedback in the oscillator.
CLOCK GENERATION AND POWER MANAGEMENT Choose C and L component values in the third overtone crystal circuit to satisfy the following conditions: • The LC components form an equivalent series resonant circuit at a frequency below the fundamental frequency. This criterion makes the circuit inductive at the fundamental frequency.
CLOCK GENERATION AND POWER MANAGEMENT (a) Series or Parallel Resonant Frequency (b) Equivalent Capacitance ω – – ------------------------ - ----------------------------------------------------------- ω 2π L – Figure 5-4. Equations for Crystal Calculations The equation in Figure 5-4(b) yields the equivalent capacitance C at the operation frequency.
CLOCK GENERATION AND POWER MANAGEMENT 220.127.116.11 Selecting Crystals When specifying crystals, consider these parameters: • Resonance and Load Capacitance — Crystals carry a parallel or series resonance specifi- cation. The two types do not differ in construction, just in test conditions and expected circuit application.
CLOCK GENERATION AND POWER MANAGEMENT An important consideration when using crystals is that the oscillator start correctly over the volt- age and temperature ranges expected in operation. Observe oscillator startup in the laboratory. Varying the load capacitors (within about ± 50%) can optimize startup characteristics versus sta- bility.
CLOCK GENERATION AND POWER MANAGEMENT Reset may be either cold (power-up) or warm. Figure 5-6 illustrates a cold reset. Assert the RES- IN input during power supply and oscillator startup. The processor’s pins assume their reset pin states a maximum of 28 CLKIN periods after CLKIN and V stabilize.
CLOCK GENERATION AND POWER MANAGEMENT CLKIN V cc and CLKIN stable to output valid 28 CLKIN periods (max) CLKOUT UCS, LCS MCS3:0 PCS6:0 T0OUT, T1OUT HLDA, ALE A19:16 AD15:0, S2:0 RD, WR, DEN DT/R, LOCK RESIN RESOUT V cc and CLKIN stable to RESIN high, RESIN high to first bus activity, approximately 32 CLKIN periods.
CLOCK GENERATION AND POWER MANAGEMENT CLKIN CLKOUT UCS, LCS MCS3:0 PCS6:0 T0OUT T1OUT HLDA, ALE A19/S6-A16 AD15:0 S2:0, RD WR, DEN DT/R LOCK RESIN RESOUT Minimum RESIN RESIN low time 4 CLKOUT high to periods. first bus activity 7 CLKOUT periods.
CLOCK GENERATION AND POWER MANAGEMENT There are three power management modes: Idle, Powerdown and Power-Save. Power-Save mode is a clock generation function, while Idle and Powerdown modes are clock distribution functions. For this discussion, Active mode is the condition of no programmed power management. Active mode operation feeds the clock signal to the CPU core and all the integrated peripherals and pow- er consumption reaches its maximum for the application.
PWRDN bit, otherwise Powerdown mode is not armed. NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 5-9. Power Control Register 5-12...
CLOCK GENERATION AND POWER MANAGEMENT Halt Cycle T4 or TI CLKOUT Internal Peripheral Clock CPU Core Clock S2:0 A1119-0A Figure 5-10. Entering Idle Mode 18.104.22.168 Bus Operation During Idle Mode DMA requests, refresh requests and HOLD requests temporarily turn on the core clocks. If the processor needs to run a DMA cycle during Idle mode, the internal core clock begins to toggle on the falling CLKOUT edge three clocks after the processor samples the DMA request pin.
CLOCK GENERATION AND POWER MANAGEMENT If the processor needs to run a refresh cycle during Idle mode, the internal core clock begins to toggle on the falling CLKOUT edge immediately after the down-counter reaches zero. After one idle T-state, the processor runs the refresh cycle. As with all other bus cycles, the BIU uses the ready, wait state generation and chip-select circuitry as necessary for refresh cycles during Idle mode.
CLOCK GENERATION AND POWER MANAGEMENT Any unmasked interrupt received by the core will return the processor to Active mode. Interrupt requests pass through the Interrupt Control Unit with an interrupt resolution time for mask and priority level checking. Then, after 1½ clocks, the core clock begins toggling. It takes an addi- tional 6 CLKOUT cycles for the core to begin the interrupt vectoring sequence.
CLOCK GENERATION AND POWER MANAGEMENT $mod186 name example_80C186_power_management_code ;FUNCTION: This function reduces CPU power consumption. SYNTAX: extern void far power_mgt(int mode); INPUTS: mode - 00 -> Active Mode 01 -> Powerdown Mode 02 -> Idle Mode 03 -> Active Mode ;...
CLOCK GENERATION AND POWER MANAGEMENT 22.214.171.124 Entering Powerdown Mode Powerdown mode is entered by executing the HLT instruction after setting the PWRDN bit in the Power Control Register (see Figure 5-9 on page 5-12). The HALT cycle turns off both the core and peripheral clocks and disables the crystal oscillator.
CLOCK GENERATION AND POWER MANAGEMENT 126.96.36.199 Leaving Powerdown Mode An NMI or reset returns the processor to Active mode. If the device leaves Powerdown mode by an NMI, a delay must follow the interrupt request to allow the crystal oscillator to stabilize before gating it to the internal phase clocks.An external timing pin sets this delay as described below.
CLOCK GENERATION AND POWER MANAGEMENT The first step in determining the proper C value is startup time characterization for the crystal oscillator circuit. This step can be done with a storage oscilloscope if you compensate for scope probe loading effects. Characterize startup over the full range of operating voltages and temper- atures.
0 1 By 4 1 0 By 8 1 1 By 16 NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 5-14. Power-Save Register 5-20...
CLOCK GENERATION AND POWER MANAGEMENT CLKOUT NOTES: 1. : Write to Power-Save Register (as viewed on the bus). 2. : Low-going edge of T3 starts new clock rate. A1124-0A Figure 5-15. Power-Save Clock Transition 188.8.131.52 Leaving Power-Save Mode Power-Save mode continues until one of three events occurs: execution clears the PSEN bit in the Power-Save Register, an unmasked interrupt occurs or an NMI occurs.
CLOCK GENERATION AND POWER MANAGEMENT $mod186 name example_PSU_code ;FUNCTION: This function reduces CPU power consumption by dividing the CPU operating frequency by a divisor. SYNTAX: extern void far power_save(int divisor); INPUTS: divisor - This variable represents F0, F1 and F2 of PWRSAV.
CLOCK GENERATION AND POWER MANAGEMENT 5.2.4 Implementing a Power Management Scheme Table 5-2 summarizes the power management options available to the user. With three ways available to reduce power consumption, here are some guidelines: • Powerdown mode reduces power consumption by several orders of magnitude. If the application goes into and out of Powerdown frequently, the power reduction can probably offset the relatively long intervals spent leaving Powerdown mode.
CHAPTER 6 CHIP-SELECT UNIT Every system requires some form of component-selection mechanism to enable the CPU to ac- cess a specific memory or peripheral device. The signal that selects the memory or peripheral de- vice is referred to as a chip-select. Besides selecting a specific device, each chip-select can be used to control the number of wait states inserted into the bus cycle.
CHIP-SELECT UNIT 27C256 74AC138 Selects 896K to 1M D7:0 Selects 768K to 896K A0:12 A1:13 D15:8 HLDA Selects 128K to 256K Selects 0 to 128K Chip-Selects Using Chip-Selects Using Addresses Directly Simple Decoder A1168-0A Figure 6-1. Common Chip-Select Generation Methods CHIP-SELECT UNIT FUNCTIONAL OVERVIEW The Chip-Select Unit (CSU) decodes bus cycle address and status information and enables the appropriate chip-select.
CHIP-SELECT UNIT Internal Address Bus = Block Size = Block Size = Block Size/4 MCS3 = Block Size/4 MCS2 = Base = Block Size/4 MCS1 = Block Size/4 MCS0 = Base Base + 0 PCS0 Base + 128 PCS1 Base + 256 PCS2 Memory/ Base + 384...
CHIP-SELECT UNIT Mapped only to the upper memory address space; selects the BOOT memory device (EPROM or Flash memory types). Mapped only to the lower memory address space; selects a static memory (SRAM) device that stores the interrupt vector table, local stack, local data, and scratch pad data.
CHIP-SELECT UNIT By combining LCS, UCS and MCS3:0, you can cover up to 786 Kbytes of memory address space. Methods such as those shown in Figure 6-1 on page 6-2 can be used to decode the remaining 256 Kbytes. The PCS6:0 chip-selects access a contiguous, 896-byte block of memory or I/O address space. Each chip-select goes active for one-seventh of the block (128 bytes).
CHIP-SELECT UNIT PROGRAMMING Four registers determine the operating characteristics of the chip-selects. The Peripheral Control Block defines the location of the Chip-Select Unit registers. Table 6-1 lists the registers and their associated programming names. Table 6-1. Chip-Select Unit Registers Control Register Alternate Register Chip-Select Affected Mnemonic...
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Programming U17:10 with values other than those shown in Table 6-2 on page 6-12 results in unreliable chip-select operation.
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Programming U17:10 with values other than those shown in Table 6.3 on page 6-13 results in unreliable chip-select operation.
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. A starting address other than an integer multiple of the block size defined in the MPCS register causes unreliable chip-select operation.
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. U19:16 must be programmed to zero for proper I/O bus cycle operation. Reading this register and the MPCS register (before writing them) enables the PCS chip-selects;...
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. A starting address other than an integer multiple of the block size defined in this register causes unreliable chip-select operation.
CHIP-SELECT UNIT The UMCS and LMCS registers can be programmed in any sequence. To program the MCS and PCS chip-selects, follow this sequence: Program the MPCS register Program the MMCS register to enable the MCS chip-selects. Program the PACS register to enable the PCS chip-selects. 6.4.2 Programming the Active Ranges The active ranges of the chip-selects are determined by a combination of their starting or ending...
CHIP-SELECT UNIT 184.108.40.206 LCS Active Range The LCS starting address is fixed at zero in memory address space; its ending address is the pro- grammed block size minus one. Table 6.3 defines the acceptable values for the field (U17:10) in the LMCS register that determines the LCS block size and ending address.
CHIP-SELECT UNIT Table 6-5. MCS Block Size and Start Address Restrictions MPCS Block Size Bits Block Size MMCS Start Address (Kbytes) Restrictions None U13 must be zero. U14:13 must be zero. U15:13 must be zero. U16:13 must be zero. U17:13 must be zero. U18:13 must be zero.
CHIP-SELECT UNIT 220.127.116.11 PCS Active Range Each PCS chip-select starts at an offset above the base address programmed in the PACS register and is active for 128 bytes. The base address can start on any 1 Kbyte memory or I/O address location.
CHIP-SELECT UNIT BUS READY R2 Control Bit READY Wait Wait State Wait State Value (R1:0) State Counter Ready A1137-0A Figure 6-11. Wait State and Ready Control Functions The R2 control bit determines whether the bus cycle completes normally (requires bus ready) or unconditionally (ignores bus ready).
When programming the PCS chip-selects active for I/O bus cycles, remember that eight bytes of I/O are reserved by Intel. These eight bytes (locations 00F8H through 00FFH) control the inter- face to an 80C187 math coprocessor. A chip-select can overlap this reserved space provided there is no intention of using the 80C187.
CHIP-SELECT UNIT CHIP-SELECTS AND BUS HOLD The Chip-Select Unit decodes only internally generated address and bus state information. An ex- ternal bus master cannot make use of the Chip-Select Unit. During HLDA, all chip-selects remain inactive. The circuit shown in Figure 6-12 allows an external bus master to access a device during bus HOLD.
CHIP-SELECT UNIT Processor ARDY SRDY EPROM SRAM Floppy 128K Disk Control A19:16 Addr DACK AD Bus 256K AD15:0 PCS1 MCS3:0 PCS0 A1138-0A Figure 6-13. Typical System 6-19...
CHIP-SELECT UNIT TITLE (Chip-Select Unit Initialization) MOD186XREF NAME CSU_EXAMPLE_1 ; External reference from this module include(PCBMAP.INC ;File declares register ;locations and names. ; Module equates ; Configuration equates INTRDY EQU 0004H ;Internal bus ready modifier EXTRDY EQU 0000H ;External bus ready modifier 0080H ;PCS Memory/IO select modifier ALLPCS EQU...
CHIP-SELECT UNIT DRAM_BASE ;window start address in Kbytes DRAM_SIZE ;window size in Kbytes DRAM_WAIT ;wait states DRAM_RDY INTRDY ;ignore bus ready ;The MPCS register is used to program both the MCS and PCS chip-selects. ;Below are the equates for the I/O peripherals (also used to program the PACS ;register.
CHIP-SELECT UNIT dx, MPCS_REG ;ready for PCS lines 4-6 ax, MPCS_VAL ;as well as MCS programming dx, al dx, MMCS_REG ;set up DRAM chip-selects ax, MMCS_VAL dx, al dx, PACS_REG ;set up I/O chip-select ax, PACS_VAL dx, al CODE ENDS ;Power-on reset code to get started ASSUME CS:POWER_ON POWER_ON SEGMENT AT 0FFFFH...
CHAPTER 7 REFRESH CONTROL UNIT The Refre h Control Unit (RCU) simplifies dynamic memory controller design with its integrat- ed address and clock counters. Figure 7-1 shows the relationship between the Bus Interface Unit and the Refresh Control Unit. Integrating the Refresh Control Unit into the processor allows an external DRAM controller to use chip-selects, wait state logic and status lines.
REFRESH CONTROL UNIT THE ROLE OF THE REFRESH CONTROL UNIT Like a DMA controller, the Refresh Control Unit runs bus cycles independent of CPU execution. Unlike a DMA controller, however, the Refresh Control Unit does not run bus cycle bursts nor does it transfer data.
REFRESH CONTROL UNIT Refresh Control BIU Refresh Unit Operation Bus Operation Refresh Request Set "E" Bit Acknowledged Execute Load Counter Memory Read From Refresh Clock Interval Register Increment Address Counter = ? Remove Executed Request Every Clock Continue Decrement Counter Generated BIU Request A1265-0A...
REFRESH CONTROL UNIT The BIU does not queue DRAM refresh requests. If the Refresh Control Unit generates another request before the BIU handles the present request, the BIU loses the present request. However, the address associated with the request is not lost. The refresh address changes only after the BIU runs a refresh bus cycle.
REFRESH CONTROL UNIT REFRESH BUS CYCLES Refresh bus cycles look exactly like ordinary memory read bus cycles except for the control sig- nals listed in Table 7-1. These signals can be ANDed in a DRAM controller to detect a refresh bus cycle.
REFRESH CONTROL UNIT T3/TW CLKOUT Muxed Column Address S2:0 NOTES: 1. CAS is unnecessary for refresh cycles only. 2. WE is necessary for write cycles only. A1267-0A Figure 7-4. Suggested DRAM Control Signal Timing Relationships The cycle begins with presentation of the row address. RAS should go active on the falling edge of T2.
REFRESH CONTROL UNIT PROGRAMMING THE REFRESH CONTROL UNIT Given a specific processor operating frequency and information about the DRAMs in the system, the user can program the Refresh Control Unit registers. 7.7.1 Calculating the Refresh Interval DRAM data sheets show DRAM refresh requirements as a number of refresh cycles necessary and the maximum period to run the cycles.
Uppermost address bits for DRAM refresh Base cycles. NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 7-6. Refresh Base Address Register 18.104.22.168 Refresh Clock Interval Register The Refresh Clock Interval Register (Figure 7-7) defines the time between refresh requests.
Sets the desired clock count between refresh Reload Value cycles. NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 7-7. Refresh Clock Interval Register 22.214.171.124 Refresh Control Register Figure 7-8 shows the Refresh Control Register.
The user cannot program these bits. NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 7-8. Refresh Control Register 7.7.3 Programming Example Example 7-1 contains sample code to initialize the Refresh Control Unit.
REFRESH CONTROL UNIT $mod186 name example_80C186_RCU_code ; FUNCTION: This function initializes the DRAM Refresh ; Control Unit to refresh the DRAM starting at dram_addr ; at clock_time intervals. ; SYNTAX: ; extern void far config_rcu(int dram_addr, int clock_time); ; INPUTS: dram_addr - Base address of DRAM to refresh clock_time - DRAM refresh rate...
REFRESH CONTROL UNIT dx, RFBASE ;set upper 7 address bits ax, _dram_addr dx, al dx, RFTIME ;set clock pre_scaler ax, _clock_time dx, al dx, RFCON ;Enable RCU ax, Enable dx, al cx, 8 ;8 dummy cycles are ;required by DRAMs di, di ;before actual use _exercise_ram:...
REFRESH CONTROL UNIT CLKOUT HOLD HLDA AD15:0 RD, WR, BHE, S2:0 DT / R, A19:16 NOTES: 1. HLDA is deasserted; signaling need to run DRAM refresh cycles less than T CLOV 2. External bus master terminates use of the bus. 3.
CHAPTER 8 INTERRUPT CONTROL UNIT The 80C186 Modular Core has a single maskable interrupt input. (See “Interrupts and Exception Handling” on page 2-39.) The Interrupt Control Unit (ICU) expands the interrupt capabilities be- yond a single input. To fulfill this function, the Interrupt Control Unit operates in either of two modes: Master or Slave.
INTERRUPT CONTROL UNIT Interrupts eliminate the need for polling by signalling the CPU that a peripheral device requires servicing. The CPU then stops executing the main task, saves its state and transfers execution to the peripheral-servicing code (the interrupt handler). At the end of the interrupt handler, the CPU’s original state is restored and execution continues at the point of interruption in the main task.
INTERRUPT CONTROL UNIT 126.96.36.199 Interrupt Masking There are circumstances in which a programmer may need to disable an interrupt source tempo- rarily (for example, while executing a time-critical section of code or servicing a high-priority task). This temporary disabling is called interrupt masking. All interrupts from the Interrupt Con- trol Unit can be masked either globally or individually.
INTERRUPT CONTROL UNIT The priority of each source is programmable. The Interrupt Control register enables the programmer to assign each source a priority that differs from the default. The priority must still be between zero (highest) and seven (lowest). Interrupt sources can be programmed to share a priority.
INTERRUPT CONTROL UNIT FUNCTIONAL OPERATION IN MASTER MODE This section covers the process in which the Interrupt Control Unit receives interrupts and asserts the maskable interrupt request to the CPU. 8.3.1 Typical Interrupt Sequence When the Interrupt Control Unit first detects an interrupt, it sets the corresponding bit in the In- terrupt Request register to indicate that the interrupt is pending.
INTERRUPT CONTROL UNIT 188.8.131.52 Priority Resolution Example This example illustrates priority resolution. Assume these initial conditions: • the Interrupt Control Unit has been initialized • no interrupts are pending • no In-Service bits are set • the Interrupt Enable bit is set •...
INTERRUPT CONTROL UNIT 184.108.40.206 Interrupts That Share a Single Source Multiple interrupt requests can share a single interrupt input to the Interrupt Control Unit. (For example, the three timers share a single input.) Although these interrupts share an input, each has its own interrupt vector.
INTERRUPT CONTROL UNIT INT0 V CC 8259A 82C59A INTA INTA0 Interrupt Control Unit INT1 V CC 8259A 82C59A INTA INTA1 A1211-A0 Figure 8-2. Using External 8259A Modules in Cascade Mode 220.127.116.11 Special Fully Nested Mode Special fully nested mode is an optional feature normally used with cascade mode. It is applicable only to INT0 and INT1.
INTERRUPT CONTROL UNIT 8.3.4 Interrupt Acknowledge Sequence During the interrupt acknowledge sequence, the Interrupt Control Unit passes the interrupt type to the CPU. The CPU then multiplies the interrupt type by four to derive the interrupt vector ad- dress in the interrupt vector table. (“Interrupt/Exception Processing” on page 2-39 describes the interrupt acknowledge sequence and Figure 2-25 on page 2-40 illustrates the interrupt vector ta- ble.) The interrupt types for all sources are fixed and unalterable (see Table 8-2).
INTERRUPT CONTROL UNIT 8.3.6 Edge and Level Triggering The external interrupts (INT3:0) can be programmed for either edge or level triggering (see “In- terrupt Control Registers” on page 8-12). Both types of triggering are active high. An edge-trig- gered interrupt is generated by a zero-to-one transition on an external interrupt pin. The pin must remain high until after the CPU acknowledges the interrupt, then must go low to reset the edge- detection circuitry.
INTERRUPT CONTROL UNIT Clocks Interrupt presented to control unit Interrupt presented to CPU INTA IDLE Cascade Mode Only INTA IDLE READ IP IDLE (5 if not cascade mode) READ CS IDLE PUSH FLAGS IDLE PUSH CS PUSH IP IDLE First instruction fetch from interrupt routine Total 55 A1212-A0...
INTERRUPT CONTROL UNIT Table 8-3. Interrupt Control Unit Registers in Master Mode (Continued) Register Name Offset Address In-Service Priority Mask Interrupt Mask Poll Status Poll 8.4.1 Interrupt Control Registers Each interrupt source has its own Interrupt Control register. The Interrupt Control register allows you to define the behavior of each interrupt source.
Defines the priority level for this source. Level NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 8-4. Interrupt Control Register for Internal Sources 8-13...
Defines the priority level for this source. Level NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 8-5. Interrupt Control Register for Noncascadable External Pins 8-14...
Defines the priority level for this source. Level NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 8-6. Interrupt Control Register for Cascadable Interrupt Pins 8-15...
Interrupt from one of the timers. NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 8-7. Interrupt Request Register 8.4.3 Interrupt Mask Register The Interrupt Mask register (Figure 8-8) contains a mask bit for each interrupt source.
Interrupt the timers. Mask NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 8-8. Interrupt Mask Register 8.4.4 Priority Mask Register The Priority Mask register (Figure 8-9) contains a three-level field that holds a priority value.
Interrupts whose priority is lower than this value are masked. NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 8-9. Priority Mask Register 8.4.5 In-Service Register The In-Service register has a bit for each interrupt source.
Interrupt In- being serviced. Service NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 8-10. In-Service Register 8.4.6 Poll and Poll Status Registers The Poll and Poll Status registers allow you to poll the Interrupt Control Unit and service inter- rupts through software.
Contains the interrupt type of the highest priority pending interrupt. NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 8-11. Poll Register 8-20...
Contains the interrupt type of the highest priority pending interrupt. NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 8-12. Poll Status Register 8.4.7...
Type whose In-Service bit is to be cleared. NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 8-13. End-of-Interrupt Register 8.4.8 Interrupt Status Register The Interrupt Status register (Figure 8-14) contains the DMA Halt bit and one bit for each timer interrupt.
Pending NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 8-14. Interrupt Status Register NOTE Do not write to the DHLT bit while Timer/Counter Unit interrupts are enabled.
INTERRUPT CONTROL UNIT INT0 V CC 8259A/ 82C59A INTA INTA 80186 Modular Core Cascade Select Address Decode A1194-A0 Figure 8-15. Interrupt Control Unit in Slave Mode 8-24...
INTERRUPT CONTROL UNIT Timer 0 Timer 1 Timer 2 Interrupt Priority Resolver Vector To External 8259A Generation Interrupt Request Logic F - Bus A1195-A0 Figure 8-16. Interrupt Sources in Slave Mode 8.5.1 Slave Mode Programming Some registers differ between Slave mode and Master mode. Slave mode adds the Interrupt Vec- tor Register;...
INTERRUPT CONTROL UNIT 18.104.22.168 Interrupt Vector Register The Interrupt Vector Register is used only in Slave mode. In Master mode, the interrupt vector types are fixed; in Slave mode they are programmable. The Interrupt Vector Register is used to specify the five most-significant bits of the interrupt vector type. The three least-significant bits are fixed (Table 8-5).
The three least-significant bits are fixed (see Table 8-5). NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 8-17. Interrupt Vector Register (Slave Mode Only) 22.214.171.124 End-Of-Interrupt Register The End-of-Interrupt (EOI) register has the same function in Slave mode as in Master mode.
Table 8-5) to these bits to issue an EOI command in slave mode. NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 8-18. End-of-Interrupt Register in Slave Mode 126.96.36.199 Other Registers The Priority Mask register is identical in Slave mode and Master mode.
INTERRUPT CONTROL UNIT 8.5.2 Interrupt Vectoring in Slave Mode In Slave mode, the external 8259A module acts as the master interrupt controller. Therefore, in- terrupt acknowledge cycles are required for every interrupt, including those from integrated pe- ripherals. During the first interrupt acknowledge cycle, the external 8259A determines which slave interrupt controller has the highest priority interrupt request.
INTERRUPT CONTROL UNIT External interrupt acknowledge cycles must be run for every maskable interrupt. Therefore, the interrupt response time for every interrupt will be 55 clocks, as shown in Figure 8-21. Clocks Interrupt presented to Interrupt Control Unit Interrupt presented to external 82C59A INTA IDLE INTA...
INTERRUPT CONTROL UNIT Set the mask bit in the Interrupt Mask register for any interrupts that you wish to disable. Example 8-1 shows sample code to initialize the Interrupt Control Unit. $mod186 name example_80C186_ICU_initialization ;This routine configures the interrupt controller to provide two cascaded ;interrupt inputs (through an external 8259A connected to INT0 and INTA0#) ;and two direct interrupt inputs connected to INT1 and INT3.
CHAPTER 9 TIMER/COUNTER UNIT The Timer/Counter Unit can be used in many applications. Some of these applications include a real-time clock, a square-wave generator and a digital one-shot. All of these can be implemented in a system design. A real-time clock can be used to update time-dependent memory variables. A square-wave generator can be used to provide a system clock tick for peripheral devices.
TIMER/COUNTER UNIT T0 In T1 In Transition Latch/ Transition Latch/ Synchronizer Synchronizer Timer 0 Registers Output Latch Counter Timer 1 Element Registers Output Latch Timer 2 Registers Interrupt Latch Clock A1292-0A Figure 9-1. Timer/Counter Unit Block Diagram...
TIMER/COUNTER UNIT Timer 0 Timer 1 Timer 2 Timer 0 Timer 1 Timer 2 Timer 0 Serviced Serviced Serviced Dead Serviced Serviced Serviced Dead Serviced T0IN T1IN T0OUT T1OUT NOTES: 1. T0IN resolution time (setup time met). 2. T1IN resolution time (setup time not met). 3.
TIMER/COUNTER UNIT Timer Enabled Done Start (EN = 1) External Clocking (EXT = 1) Retrigger (RTG = 1) Lo to Hi Lo to Hi Timer Input transition on input transition on input at High Level pin since last pin since last service service Clear Count...
TIMER/COUNTER UNIT Continued From "A" Alternating Maxcount Regs (ALT = 1) Using Counter = (Use"A") (Use"B") Maxcount A Compare "A" (RIU = 0) Counter = Counter = Compare "A" Compare "B" Done Pulse TOUT Pin Set RIU Bit Clear RIU Bit Low For 1 Clock TOUT Pin Driven Low TOUT Pin Driven High...
TIMER/COUNTER UNIT When configured for internal clocking, the Timer/Counter Unit uses the input pins either to en- able timer counting or to retrigger the associated timer. Externally, a timer increments on low-to- high transitions on its input pin (up to ¼ CLKOUT frequency). Timers 0 and 1 each have a single output pin.
If MC is clear, the counter has not reached a maximum count. NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 9-5. Timer 0 and Timer 1 Control Registers...
(clear the EN bit) after each counting sequence. NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 9-5. Timer 0 and Timer 1 Control Registers (Continued)
Clear to disable the counter (clear the EN bit) after each counting sequence. NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 9-6. Timer 2 Control Register...
TIMER/COUNTER UNIT Register Name: Timer Count Register Register Mnemonic: T0CNT, T1CNT, T2CNT Register Function: Contains the current timer count. A1299-0A Reset Bit Name Function Mnemonic State TC15:0 Timer Count XXXXH Contains the current count of the associated Value timer. Figure 9-7. Timer Count Registers 9-10...
TIMER/COUNTER UNIT Register Name: Timer Maxcount Compare Register Register Mnemonic: T0CMPA, T0CMPB, T1CMPA, T1CMPB, T2CMPA Register Function: Contains timer maximum count value. A1300-0A Reset Bit Name Function Mnemonic State TC15:0 Timer XXXXH Contains the maximum value a timer will count Compare to before resetting its Count register to zero.
TIMER/COUNTER UNIT 9.2.2 Clock Sources The 16-bit Timer Count register increments once for each timer event. A timer event can be a low-to-high transition on a timer input pin (Timers 0 and 1), a pulse generated every fourth CPU clock (all timers) or a timeout of Timer 2 (Timers 0 and 1). Up to 65536 (2 ) events can be count- Timers 0 and 1 can be programmed to count low-to-high transitions on their input pins as timer events by setting the External (EXT) bit in their control registers.
TIMER/COUNTER UNIT The timer counting from its initial count (usually zero) to its maximum count (either Maxcount Compare A or B) and resetting to zero defines one timing cycle. A Maxcount Compare value of 0 implies a maximum count of 65536, a Maxcount Compare value of 1 implies a maximum count of 1, etc.
TIMER/COUNTER UNIT Table 9-2. Timer Retriggering Timer Operation Timer counts internal events, if input pin remains high. Timer counts internal events; count resets to zero on every low-to-high transition on the input pin. Timer input acts as clock source. When the EXT bit is clear and the RTG bit is set, every low-to-high transition on the timer input pin causes the Count register to reset to zero.
TIMER/COUNTER UNIT Timer 0 Serviced Internal Count Value Maxcount - 1 TxOUT Pin NOTE: 1. T CLOV1 A1301-0A Figure 9-9. TxOUT Signal Timing In dual maximum count mode, the timer output pin indicates which Maxcount Compare register is currently in use. A low output indicates Maxcount Compare B, and a high output indicates Maxcount Compare A (see Figure 9-4 on page 9-6).
TIMER/COUNTER UNIT The input pins for Timers 0 and 1 provide an alternate method for enabling and disabling timer counting. When using internal clocking, the input pin can be programmed either to enable the tim- er or to reset the timer count, depending on the state of the Retrigger (RTG) bit in the control reg- ister.
TIMER/COUNTER UNIT 9.3.2 Synchronization and Maximum Frequency All timer inputs are latched and synchronized with the CPU clock. Because of the internal logic required to synchronize the external signals, and the multiplexing of the counter element, the Timer/Counter Unit can operate only up to ¼ of the CLKOUT frequency. Clocking at greater fre- quencies will result in missed clocks.
TIMER/COUNTER UNIT $mod186 name example_80186_family_timer_code ;FUNCTION: This function sets up the timer and interrupt controller to cause the timer to generate an interrupt every 10 milliseconds and to service interrupts to implement a real time clock. Timer 2 is used in this example because no input or output signals are required.
TIMER/COUNTER UNIT lib_80186 segment public ’code’ assume cs:lib_80186, ds:data public _set_time _set_time proc far push ;save caller’s bp bp, sp ;get current top of stack hour equ word ptr[bp+6] ;get parameters off stack minute equ word ptr[bp+8] second equ word ptr[bp+10] T2Compare equ word ptr[bp+12] push ;save registers used...
TIMER/COUNTER UNIT ;enable interrupts ;restore saved registers ;restore caller’s bp _set_time endp timer_2_interrupt_routine proc far push ;save registers used push _msec, 99 ;has 1 sec passed? bump_second ;if above or equal... _msec short reset_int_ctl bump_second: _msec, 0 ;reset millisecond _minute, 59 ;has 1 minute passed? bump_minute _second...
TIMER/COUNTER UNIT $mod186 name example_timer1_square_wave_code ;FUNCTION: This function generates a square wave of given frequency and duty cycle on Timer 1 output pin. SYNTAX: extern void far clock(int mark, int space) INPUTS: mark - This is the mark (1) time. space - This is the space (0) time.
TIMER/COUNTER UNIT ;restore saved registers ;restore caller’s bp _clock endp lib_80186 ends Example 9-2. Configuring a Square-Wave Generator (Continued) $mod186 name example_timer1_1_shot_code ; FUNCTION: This function generates an active-low one-shot pulse on Timer 1 output pin. ; SYNTAX: extern void far one_shot(int CMPB); ;...
TIMER/COUNTER UNIT _CMPB equ word ptr[bp+6] ;get parameter off the stack push ;save registers that will be push ;modified dx, T1CNT ;Clear Timer 1 Counter ax, ax dx, al dx, T1CMPA ;set time before t_shot to 0 ax, 1 dx, al dx, T1CMPB ;set pulse time ax, _CMPB...
CHAPTER 10 DIRECT MEMORY ACCESS UNIT In many applications, large blocks of data must be transferred between memory and I/O space. A disk drive, for example, usually reads and writes data in blocks that may be thousands of bytes long. If the CPU were required to handle each byte of the transfer, the main tasks would suffer a severe performance penalty.
DIRECT MEMORY ACCESS UNIT When the DMA request is granted, the Bus Interface Unit provides the bus signals for the DMA transfer, while the DMA channel provides the address information for the source and destination devices. The DMA Unit does not provide a discrete DMA acknowledge signal, unlike other DMA controller chips (an acknowledge can be synthesized, however).
DIRECT MEMORY ACCESS UNIT 10.1.1.1 DMA Transfer Directions The source and destination addresses for a DMA transfer are programmable and can be in either memory or I/O space. DMA transfers can be programmed for any of the following four direc- tions: •...
DIRECT MEMORY ACCESS UNIT 10.1.4 External Requests External DMA requests are asserted on the DRQ pins. The DRQ pins are sampled on the falling edge of CLKOUT. It takes a minimum of four clocks before the DMA cycle is initiated by the BIU (see Figure 10-2).
DIRECT MEMORY ACCESS UNIT 10.1.4.1 Source Synchronization A typical source-synchronized transfer is shown in Figure 10-3. Most DMA-driven peripherals deassert their DRQ line only after the DMA transfer has begun. The DRQ signal must be deas- serted at least four clocks before the end of the DMA transfer (at the T1 state of the deposit phase) to prevent another DMA cycle from occurring.
DIRECT MEMORY ACCESS UNIT Fetch Cycle Deposit Cycle CLKOUT (Case 1) (Case 2) NOTES: 1. Current destination synchronized transfer will not be immediately followed by another DMA transfer. 2. Current destination synchronized transfer will be immediately followed by another DMA transfer. A1189-0A Figure 10-4.
DIRECT MEMORY ACCESS UNIT 10.1.6 DMA Transfer Counts Each DMA Unit maintains a programmable 16-bit transfer count value that controls the total number of transfers the channel runs. The transfer count is decremented by one after each transfer (regardless of data size). The DMA channel can be programmed to terminate transfers when the transfer count reaches zero (also referred to as terminal count).
DIRECT MEMORY ACCESS UNIT 10.1.8 DMA Unit Interrupts Each DMA channel can be programmed to generate an interrupt request when its transfer count reaches zero. 10.1.9 DMA Cycles and the BIU The DMA Unit uses the Bus Interface Unit to perform its transfers. When the DMA Unit has a pending request, it signals the BIU.
DIRECT MEMORY ACCESS UNIT The last point is extremely important when the two channels use different synchronization. For example, consider the case in which channel 1 is programmed for high priority and destination synchronization and channel 0 is programmed for low priority and source synchronization. If a DMA request occurs for both channels simultaneously, channel 1 performs the first transfer.
DIRECT MEMORY ACCESS UNIT Both Requests Asserted Channel Etc. Priority Channel 1 Channel 0 Channel 1 Channel 0 Synch Channel Etc. Priority High Channel 0 Channel 0 Channel 1 Channel 1 Synch Channel 0 Completes All Transfers Channel Etc. Priority High Channel 0 Channel 1...
DMA transfer. Address NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 10-7. DMA Source Pointer (High-Order Bits) 10-11...
DIRECT MEMORY ACCESS UNIT Register Name: DMA Source Address Pointer (Low) Register Mnemonic: DxSRCL Register Function: Contains the lower 16 bits of the DMA Source pointer. A1177-0A Reset Bit Name Function Mnemonic State DSA15:0 XXXXH DSA15:0 are driven on the lower 16 bits of the Source address bus during the fetch phase of a DMA Address...
DMA transfer. Address NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 10-9. DMA Destination Pointer (High-Order Bits) 10-13...
DIRECT MEMORY ACCESS UNIT Register Name: DMA Destination Address Pointer (Low) Register Mnemonic: DxDSTL Register Function: Contains the lower 16 bits of the DMA Destination pointer. A1179-0A Reset Bit Name Function Mnemonic State DDA15:0 XXXXH DDA15:0 are driven on the lower 16 bits of the Destination address bus during the deposit phase of a DMA Address...
(See Note.) NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. A pointer remains constant if its increment and decrement bits are equal.
(SYN1:0 = 01). NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 10-11. DMA Control Register (Continued) 10-16...
Select device ignore the WORD bit. NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a logic zero to ensure compatibility with future Intel products. Figure 10-11. DMA Control Register (Continued) 10.2.1.3 Selecting the Source of DMA Requests DMA requests can come from either an internal source (Timer 2) or an external source.
DIRECT MEMORY ACCESS UNIT 10.2.1.4 Arming the DMA Channel Each DMA channel must be armed before it can recognize DMA requests. A channel is armed by setting its STRT (Start) bit in the DMA Control Register (Figure 10-11 on page 10-15). The STRT bit can be modified only if the CHG (Change Start) bit is set at the same time.
DIRECT MEMORY ACCESS UNIT Register Name: DMA Transfer Count Register Mnemonic: DxTC Register Function: Contains the DMA channel’s transfer count. A1172-0A Reset Bit Name Function Mnemonic State TC15:0 Transfer XXXXH Contains the transfer count for a DMA channel. Count This value is decremented by one after each transfer.
DIRECT MEMORY ACCESS UNIT 10.2.2 Suspension of DMA Transfers Whenever the CPU receives an NMI, all DMA activity is suspended at the end of the current transfer. The CPU suspends DMA activity by setting the DHLT bit in the Interrupt Status Regis- ter (Figure 8-14 on page 8-23).
DIRECT MEMORY ACCESS UNIT 10.3.2 DMA Latency DMA Latency is the delay between a DMA request being asserted and the DMA cycle being run. The DMA latency for a channel is controlled by many factors: • Bus HOLD — Bus HOLD takes precedence over internal DMA requests. Using bus HOLD will degrade DMA latency.
DIRECT MEMORY ACCESS UNIT 10.3.4 Generating a DMA Acknowledge The DMA channels do not provide a distinct DMA acknowledge signal. A chip-select line can be programmed to activate for the memory or I/O range that requires the acknowledge. The chip- select must be programmed to activate only when a DMA is in progress.
DIRECT MEMORY ACCESS UNIT $MOD186 name DMA_EXAMPLE_1 ; This example shows code necessary to set up two DMA channels. ; One channel performs an unsynchronized transfer from memory to memory. ; The second channel is used by a hard disk controller located in ;...
DIRECT MEMORY ACCESS UNIT DX, D0DSTH AX, BX ; GET HIGH NIBBLE DX, AX ; THE POINTER ADDRESSES HAVE BEEN SET UP. NOW WE SET UP THE TRANSFER COUNT. AX, 29 ; THE MESSAGE IS 29 BYTES LONG. DX, D0TC ;...
DIRECT MEMORY ACCESS UNIT AX, 512 ; THE DISK READS IN 512 BYTE SECTORS DX, D1TC ; XFER COUNT REG DX, AX ; NOW WE NEED TO SET THE PARAMETERS FOR THE CHANNEL AS FOLLOWS: DESTINATION SOURCE ----------- ------ MEMORY SPACE I/O SPACE INCREMENT PTR CONSTANT PTR...
DIRECT MEMORY ACCESS UNIT $mod186 name DMA_EXAMPLE_1 ; This example sets up the DMA Unit to perform a transfer from memory to ; I/O space every 22 uS. The data is sent to an A/D converter. ; It is assumed that the constants for PCB register addresses are ;...
DIRECT MEMORY ACCESS UNIT ; NOW WE NEED TO SET THE PARAMETERS FOR THE CHANNEL AS FOLLOWS: DESTINATION SOURCE ----------- ------ I/O SPACE MEMORY SPACE CONSTANT PTR INCREMENT PTR ; TERMINATE ON TC, INTERRUPT, SOURCE SYNCHRONIZE, INTERNAL REQUESTS, ; LOW PRIORITY RELATIVE TO CHANNEL 1, BYTE XFERS. AX, 0001011101010110B DX, D0CON DX, AX...
80C187 has only a 5-volt rating. Please refer to the current data sheets for details. To execute numerics instructions, the 80C186EA must exit reset in Numerics Mode. The proces- sor checks its TEST pin at reset and automatically enters Numerics Mode if the math coprocessor is present.
MATH COPROCESSING The core has an Escape Trap (ET) bit in the PCB Relocation Register (Figure 4-1 on page 4-2) to control the availability of math coprocessing. If the ET bit is set, an attempted numerics execution results in a Type 7 interrupt. The 80C187 will not work with the 8-bit bus version of the processor because all 80C187 accesses must be 16-bit.
MATH COPROCESSING 188.8.131.52 Data Transfer Instructions Data transfer instructions move operands between elements of the 80C187 register stack or be- tween stack top and memory. Instructions can convert any data type to temporary real and load it onto the stack in a single operation. Conversely, instructions can convert a temporary real oper- and on the stack to any data type and store it to memory in a single operation.
MATH COPROCESSING Available data types include temporary real, long real, short real, short integer and word integer. The 80C187 performs automatic type conversion to temporary real. Table 11-2. 80C187 Arithmetic Instructions Addition Division FADD Add real FDIV Divide real FADDP Add real and pop FDIVP Divide real and pop...
MATH COPROCESSING 184.108.40.206 Comparison Instructions Each comparison instruction (see Table 11-3) analyzes the stack top element, often in relationship to another operand. Then it reports the result in the Status Word condition code. The basic oper- ations are compare, test (compare with zero) and examine (report tag, sign and normalization). Table 11-3.
MATH COPROCESSING 220.127.116.11 Constant Instructions Each constant instruction (see Table 11-5) loads a commonly used constant onto the stack. The values have full 80-bit precision and are accurate to about 19 decimal digits. Since a temporary real constant occupies 10 memory bytes, the constant instructions, only 2 bytes long, save mem- ory space.
MATH COPROCESSING 11.3.2 80C187 Data Types The microprocessor/math coprocessor combination supports seven data types: • Word Integer — A signed 16-bit numeric value. All operations assume a 2’s complement representation. • Short Integer — A signed 32-bit numeric value (double word). All operations assume a 2’s complement representation.
MATH COPROCESSING Increasing Significance Word (Two's Complement) Magnitude Integer Short (Two's Complement) Magnitude Integer (Two's Long Magnitude Complement) Integer Magnitude Packed 10 d 9 Decimal Short Biased Significand Real Exponent Long Biased Significand Exponent Real Temporary Biased Significand Exponent Real 64 63 NOTES: S = Sign bit (0 = positive, 1 = negative)
MATH COPROCESSING 11.4.1 Clocking the 80C187 The microprocessor and math coprocessor operate asynchronously, and their clock rates may dif- fer. The 80C187 has a CKM pin that determines whether it uses the input clock directly or divided by two. Direct clocking works up to 12.5 MHz, which makes it convenient to feed the clock input from the microprocessor’s CLKOUT pin.
MATH COPROCESSING Bus cycles involving the 80C187 Math Coprocessor behave exactly like other I/O bus cycles with respect to the processor’s control pins. See “System Design Tips” for information on integrating the 80C187 into the overall system. 11.4.3 System Design Tips All 80C187 operations require that bus ready be asserted.
MATH COPROCESSING Latch External A15:0 Oscillator Buffer D15:8 AD15:0 T OE CLKOUT 80C187 80C186 Modular Core RESET Buffer RESOUT D7:0 NPWR NPRD BUSY BUSY ERROR ERROR PEREQ PEREQ NPS1 NPS2 DT/R D15:0 A1255-01 Figure 11-3. 80C187 Configuration with a Partially Buffered Bus 11-12...
MATH COPROCESSING 11.4.4 Exception Trapping The 80C187 detects six error conditions that can occur during instruction execution. The 80C187 can apply default fix-ups or signal exceptions to the microprocessor’s ERROR pin. The processor tests ERROR at the beginning of numerics instructions, so it traps an exception on the next at- tempted numerics instruction after it occurs.
MATH COPROCESSING 80C186 Modular Core ERROR RESOUT CS x INT x Latch BUSY PEREQ A19:A16 AD15:0 CLKOUT D15:0 D15:0 CMD1 NPWR A19:0 CMD0 NPRD 80C187 NPS1 PEREQ BUSY NPS2 ERROR RESET A1256-01 Figure 11-4. 80C187 Exception Trapping via Processor Interrupt Pin 11-14...
MATH COPROCESSING $mod186 name example_80C187_init ;FUNCTION: This function initializes the 80C187 numerics coprocessor. ;SYNTAX: extern unsigned char far 187_init(void); ;INPUTS: None ;OUTPUTS: unsigned char - 0000h -> False -> coprocessor not initialized ffffh -> True -> coprocessor initialized ;NOTE: Parameters are passed on the stack as required by high-level languages.
The results of the computation are the coordinates x and y expressed as 32-bit reals. ;NOTES: This routine is coded for Intel ASM86. It is not set up as an HLL-callable routine. This code assumes that the 80C187 has already been initialized.
CHAPTER 12 ONCE MODE ONCE (pronounced “ahnce”) Mode provides the ability to three-state all output, bidirectional, or weakly held high/low pins except OSCOUT. To allow device operation with a crystal network, OSCOUT does not three-state. ONCE Mode electrically isolates the device from the rest of the board logic. This isolation allows a bed-of-nails tester to drive the device pins directly for more accurate and thorough testing.
ONCE MODE RESIN All output, bidirectional, weakly held pins except OSCOUT NOTES: 1. Entering ONCE Mode. 2. Latching ONCE Mode. 3. Leaving ONCE Mode (assuming 2 occurred). A1258-0A Figure 12-1. Entering/Leaving ONCE Mode 12-2...
80C186 Instruction Set Additions and Extensions...
APPENDIX A 80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS The 80C186 Modular Core family instruction set differs from the original 8086/8088 instruction set in two ways. First, several instructions that were not available in the 8086/8088 instruction set have been added. Second, several 8086/8088 instructions have been enhanced for the 80C186 Modular Core family instruction set.
80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS A.1.2 String Instructions INS source_string, port INS (in string) performs block input from an I/O port to memory. The port address is placed in the DX register. The memory address is placed in the DI register. This instruction uses the ES segment register (which cannot be overridden).
80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS The following listing gives the formal definition of the ENTER instruction for all cases. LEVEL denotes the value of the second operand. Push BP Set a temporary value FRAME_PTR: = SP If LEVEL > 0 then Repeat (LEVEL - 1) times: BP:=BP - 2 Push the word pointed to by BP...
80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS Main Program (Lexical Level 1) Procedure A (Lexical Level 2) Procedure B (Lexical Level 3) Procedure C (Lexical Level 3) Procedure D (Lexical Level 4) A1001-0A Figure A-2. Variable Access in Nested Procedures The first ENTER, executed in the Main Program, allocates dynamic storage space for Main, but no pointers are copied.
80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS Old BP Display A BPA* Dynamic Storage A *BPA = BP Value for Procedure A A1003-0A Figure A-4. Stack Frame for Procedure A at Level 2 After Procedure A calls Procedure B, ENTER creates the display for Procedure B. The first word of the display points to the previous value of BP (BPA).
80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS Old BP Display B Dynamic Storage B A1004-0A Figure A-5. Stack Frame for Procedure B at Level 3 Called from A...
80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS Old BP Display C Dynamic Storage C A1005-0A Figure A-6. Stack Frame for Procedure C at Level 3 Called from B LEAVE LEAVE reverses the action of the most recent ENTER instruction. It collapses the last stack frame created.
80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS BOUND register, address BOUND verifies that the signed value in the specified register lies within specified limits. If the value does not lie within the bounds, an array bounds exception (type 5) occurs. BOUND is useful for checking array bounds before attempting to access an array element.
80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS A.2.2 Arithmetic Instructions IMUL destination, source, data IMUL (integer immediate multiply, signed) allows a value to be multiplied by an immediate op- erand. IMUL requires three operands. The first, destination, is the register where the result will be placed.
80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS A.2.3.2 Rotate Instructions ROL destination, count ROL (immediate rotate left) rotates the destination byte or word left by an immediate value. ROL has two operands. The first, destination, is the effective address to be rotated. The second, count, is an immediate byte value representing the number of rotations to be made.
APPENDIX B INPUT SYNCHRONIZATION Many input signals to an embedded processor are asynchronous. Asynchronous signals do not re- quire a specified setup or hold time to ensure the device does not incur a failure. However, asyn- chronous setup and hold times are specified in the data sheet to ensure recognition. Associated with each of these inputs is a synchronizing circuit (see Figure B-1) that samples the asynchro- nous signal and synchronizes it to the internal operating clock.
As the sampling window gets smaller, the number of times an asynchro- nous transition occurs during the sampling window drops. ASYNCHRONOUS PINS The 80C186EA/80C188EA inputs that use the two-stage synchronization circuit are T0IN, T1IN, NMI, TEST/BUSY, INT3:0, HOLD, DRQ0 and DRQ1.
APPENDIX C INSTRUCTION SET DESCRIPTIONS This appendix provides reference information for the 80C186 Modular Core family instruction set. Tables C-1 through C-3 define the variables used in Table C-4, which lists the instructions with their descriptions and operations. Table C-1. Instruction Format Variables Variable Description dest...
INSTRUCTION SET DESCRIPTIONS Table C-2. Instruction Operands Operand Description An 8- or 16-bit general register. reg16 An 16-bit general register. seg-reg A segment register. accum Register AX or AL immed A constant in the range 0–FFFFH. immed8 A constant in the range 0–FFH. An 8- or 16-bit memory location.
INSTRUCTION SET DESCRIPTIONS Table C-3. Flag Bit Functions Name Function Auxiliary Flag: Set on carry from or borrow to the low order four bits of AL; cleared otherwise. Carry Flag: Set on high-order bit carry or borrow; cleared otherwise. Direction Flag: Causes string instructions to auto decrement the appropriate index register when set.
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set Flags Name Description Operation Affected ü ASCII Adjust for Addition: ü ((AL) and 0FH) > 9 or (AF) = 1 then DF – Changes the contents of register AL to (AL) ← (AL) + 6 IF –...
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected ü ASCII Adjust for Subtraction: ü ((AL) and 0FH) > 9 or (AF) = 1 then DF – Corrects the result of a previous (AL) ← (AL) – 6 IF –...
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected ü (dest) ← (dest) + (src) Addition: ü ADD dest , src DF – Sums two operands, which may be IF – ü bytes or words, replaces the ü...
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected BOUND Detect Value Out of Range: AF – ((dest) < (src) or (dest) > ((src) + 2) CF – BOUND dest , src then DF – Provides array bounds checking in (SP) ←...
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected Convert Byte to Word: AF – (AL) < 80H CF – then DF – Extends the sign of the byte in register (AH) ← 0 IF – AL throughout register AH.
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected (IF) ← 0 Clear Interrupt-enable Flag: AF – CF – DF – ü Zeroes the interrupt-enable flag (IF). When the interrupt-enable flag is OF – cleared, the 8086 and 8088 do not PF –...
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected ü Compare: (dest) – (src) ü CMP dest , src DF – Subtracts the source from the desti- IF – ü nation, which may be bytes or words, ü...
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected Convert Word to Doubleword: AF – (AX) < 8000H CF – then DF – Extends the sign of the word in register (DX) ← 0 IF – AX throughout register DX.
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected ü (dest) ← (dest) – 1 Decrement: CF – DEC dest DF – Subtracts one from the destination IF – ü operand. The operand may be a byte ü...
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected Divide: When Source Operand is a Byte: AF ? CF ? (temp) ← (byte-src) DIV src DF – Performs an unsigned division of the IF – (temp) / (AX) > FFH accumulator (and its extension) by the OF ? then (type 0 interrupt is generated)
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected (SP) ← (SP) – 2 ENTER Procedure Entry: AF – ((SP) + 1:(SP)) ← (BP) CF – ENTER locals, levels (FP) ← (SP) DF – Executes the calling sequence for a IF –...
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected Halt: None AF – CF – DF – Causes the CPU to enter the halt IF – state. The processor leaves the halt OF – state upon activation of the RESET PF –...
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected IDIV Integer Divide: When Source Operand is a Byte: AF ? CF ? (temp) ← (byte-src) IDIV src DF – Performs a signed division of the IF – (temp) / (AX) >...
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected IMUL Integer Multiply: When Source Operand is a Byte: AF ? ü (AX) ← (byte-src) × (AL) IMUL src DF – Performs a signed multiplication of the IF –...
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected ü (dest) ← (dest) + 1 Increment: CF – INC dest DF – Adds one to the destination operand. IF – ü The operand may be byte or a word ü...
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected (SP) ← (SP) – 2 Interrupt: AF – ((SP) + 1:(SP)) ← FLAGS CF – INT interrupt-type (IF) ← 0 DF – ü Activates the interrupt procedure (TF) ←...
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected INTO Interrupt on Overflow: AF – (OF) = 1 CF – INTO then DF – Generates a software interrupt if the (SP) ← (SP) – 2 IF – overflow flag (OF) is set;...
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected Jump on Above or Equal: AF – Jump on Not Below: (CF) = 0 CF – then DF – JAE disp8 (IP) ← (IP) + disp8 (sign-ext to 16 bits) IF –...
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected JCXZ Jump if CX Zero: AF – (CX) = 0 CF – JCXZ disp8 then DF – Transfers control to the target location (IP) ← (IP) + disp8 (sign-ext to 16 bits) IF –...
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected Jump on Less Than: AF – (SF) ≠ (OF) JNGE Jump on Not Greater Than or Equal: CF – then DF – JL disp8 (IP) ← (IP) + disp8 (sign-ext to 16 bits) IF –...
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected Jump on Not Equal: AF – Jump on Not Zero: (ZF) = 0 CF – then DF – JNE disp8 (IP) ← (IP) + disp8 (sign-ext to 16 bits) IF –...
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected Jump on Overflow: AF – (OF) = 1 CF – JO disp8 then DF – Transfers control to the target location (IP) ← (IP) + disp8 (sign-ext to 16 bits) IF –...
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected (dest) ← (EA) Load Pointer Using DS: AF – (DS) ← (EA + 2) CF – LDS dest, src DF – Transfers a 32-bit pointer variable from IF –...
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected (dest) ← (EA) Load Pointer Using ES: AF – (ES) ← (EA + 2) CF – LES dest, src DF – Transfers a 32-bit pointer variable from IF –...
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected LODS Load String (Byte or Word): When Source Operand is a Byte: AF – CF – (AL) ← (src-string) LODS src-string DF – Transfers the byte or word string IF –...
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected (CX) ← (CX) – 1 LOOPNE Loop While Not Equal: AF – LOOPNZ Loop While Not Zero: CF – (ZF) = 0 and (CX) ≠ 0 DF – LOOPNE disp8 then IF –...
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected (dest-string) ← (src-string) MOVS Move String: AF – CF – MOVS dest-string, src-string DF – Transfers a byte or a word from the IF – source string (addressed by SI) to the OF –...
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected ü Negate: When Source Operand is a Byte: ü (dest) ← FFH – (dest) NEG dest DF – (dest) ← (dest) + 1 (affecting flags) Subtracts the destination operand, IF –...
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected (dest) ← (dest) or (src) Logical OR: AF ? ü (CF) ← 0 OR dest,src (OF) ← 0 DF – Performs the logical "inclusive or" of IF – ü...
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected (dst) ← (src) OUTS Out String: AF – CF – OUTS port, src_string DF – Performs block output from memory to IF – an I/O port. The port address is placed OF –...
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected (DI) ← ((SP) + 1:(SP)) POPA Pop All: AF – (SP) ← (SP) + 2 CF – POPA (SI) ← ((SP) + 1:(SP)) DF – Pops all data, pointer, and index (SP) ←...
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected temp ← (SP) PUSHA Push All: AF – (SP) ← (SP) – 2 CF – PUSHA ((SP) + 1:(SP)) ← (AX) DF – Pushes all data, pointer, and index (SP) ←...
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected (temp) ← count Rotate Through Carry Left: AF – ü do while (temp) ≠ 0 RCL dest, count (tmpcf) ← (CF) DF – Rotates the bits in the byte or word (CF) ←...
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected do while (CX) ≠ 0 Repeat: AF – REPE Repeat While Equal: service pending interrupts (if any) CF – REPZ Repeat While Zero: execute primitive string DF – REPNE Repeat While Not Equal: Operation in succeeding byte...
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected (IP) ← ((SP) = 1:(SP)) Return: AF – (SP) ← (SP) + 2 CF – RET optional-pop-value DF – Transfers control from a procedure inter-segment IF – back to the instruction following the then OF –...
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected (temp) ← count Rotate Right: AF – ü do while (temp) ≠ 0 ROR dest, count (CF) ← low-order bit of (dest) DF – Operates similar to ROL except that (dest) ←...
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected (temp) ← count Shift Logical Left: AF ? ü do while (temp) ≠ 0 Shift Arithmetic Left: (CF) ← high-order bit of (dest) DF – SHL dest, count (dest) ←...
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected ü Subtract With Borrow: ü (CF) = 1 SBB dest, src then DF – Subtracts the source from the desti- (dest) = (dest) – (src) – 1 IF –...
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected ü SCAS Scan String: When Source Operand is a Byte: ü SCAS dest-string (AL) – (byte-string) DF – Subtracts the destination string IF – (DF) = 0 ü...
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected (temp) ← count Shift Logical Right: AF ? ü do while (temp) ≠ 0 SHR dest, src (CF) ← low-order bit of (dest) DF – Shifts the bits in the destination (dest) ←...
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected (IF) ← 1 Set Interrupt-enable Flag: AF – CF – DF – ü Sets IF to 1, enabling processor recognition of maskable interrupt OF – requests appearing on the INTR line. PF –...
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected ü (dest) ← (dest) – (src) Subtract: ü SUB dest, src DF – The source operand is subtracted from IF – ü the destination operand, and the result ü...
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected WAIT Wait: None AF – CF – WAIT DF – Causes the CPU to enter the wait state IF – while its test line is not active. OF –...
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Flags Name Description Operation Affected AL ← ((BX) + (AL)) XLAT Translate: AF – CF – XLAT translate-table DF – Replaces a byte in the AL register with IF – a byte from a 256-byte, user-coded OF –...
Instruction Set Opcodes and Clock Cycles...
APPENDIX D INSTRUCTION SET OPCODES AND CLOCK CYCLES This appendix provides reference information for the 80C186 Modular Core family instruction set. Table D-1 defines the variables used in Table D-2, which lists the instructions with their for- mats and execution times. Table D-3 is a guide for decoding machine instructions. Table D-4 is a guide for encoding instruction mnemonics, and Table D-5 defines Table D-4 abbreviations.
INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-2. Instruction Set Summary Function Format Clocks Notes DATA TRANSFER INSTRUCTIONS MOV = Move register to register/memory 1 0 0 0 1 0 0 w mod reg r/m 2/12 register/memory to register 1 0 0 0 1 0 1 w mod reg r/m immediate to register/memory 1 1 0 0 0 1 1 w...
INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-2. Instruction Set Summary (Continued) Function Format Clocks Notes DATA TRANSFER INSTRUCTIONS (Continued) LEA = Load EA to register 1 0 0 0 1 1 0 1 mod reg r/m LDS = Load pointer to DS 1 1 0 0 0 1 0 1 mod reg r/m (mod ?11)
INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-2. Instruction Set Summary (Continued) Function Format Clocks Notes ARITHMETIC INSTRUCTIONS (Continued) SUB = Subtract reg/memory with register to either 0 0 1 0 1 0 d w mod reg r/m 3/10 immediate from register/memory 1 0 0 0 0 0 s w mod 101 r/m data...
INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-2. Instruction Set Summary (Continued) Function Format Clocks Notes ARITHMETIC INSTRUCTIONS (Continued) AAM = ASCII adjust for multiply 1 1 0 1 0 1 0 0 0 0 0 0 1 0 1 0 DIV = Divide (unsigned) 1 1 1 1 0 1 1 w mod 110 r/m...
INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-2. Instruction Set Summary (Continued) Function Format Clocks Notes BIT MANIPULATION INSTRUCTIONS (Continued) TEST= And function to flags, no result register/memory and register 1 0 0 0 0 1 0 w mod reg r/m 3/10 immediate data and register/memory 1 1 1 1 0 1 1 w...
INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-2. Instruction Set Summary (Continued) Function Format Clocks Notes PROGRAM TRANSFER INSTRUCTIONS Conditional Transfers — jump if: JE/JZ= equal/zero 0 1 1 1 0 1 0 0 disp 4/13 JL/JNGE = less/not greater or equal 0 1 1 1 1 1 0 0 disp 4/13...
INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-2. Instruction Set Summary (Continued) Function Format Clocks Notes PROGRAM TRANSFER INSTRUCTIONS (Continued) RET = Return from procedure within segment 1 1 0 0 0 0 1 1 within segment adding immed to SP 1 1 0 0 0 0 1 0 data-low data-high...
INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-2. Instruction Set Summary (Continued) Function Format Clocks Notes PROCESSOR CONTROL INSTRUCTIONS CLC = Clear carry 1 1 1 1 1 0 0 0 CMC = Complement carry 1 1 1 1 0 1 0 1 STC = Set carry 1 1 1 1 1 0 0 1 CLD = Clear direction...
INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-3. Machine Instruction Decoding Guide (Continued) Byte 1 Byte 2 Bytes 3–6 ASM-86 Instruction Format Binary 0000 1001 mod reg r/m (disp-lo),(disp-hi) reg16/mem16,reg16 0000 1010 mod reg r/m (disp-lo),(disp-hi) reg8,reg8/mem8 0000 1011 mod reg r/m (disp-lo),(disp-hi) reg16,reg16/mem16 0000 1100...
INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-3. Machine Instruction Decoding Guide (Continued) Byte 1 Byte 2 Bytes 3–6 ASM-86 Instruction Format Binary 0010 1110 (segment override prefix) 0010 1111 0011 0000 mod reg r/m (disp-lo),(disp-hi) reg8/mem8,reg8 0011 0001 mod reg r/m (disp-lo),(disp-hi) reg16/mem16,reg16 0011 0010...
INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-5. Abbreviations for Mnemonic Encoding Matrix Abbr Definition Abbr Definition Abbr Definition Abbr Definition byte operation immediate to accumulator memory to CPU register direct indirect EA is second byte variable from CPU register immediate byte, sign extended short intrasegment word operation...