Cpwt - Intel 82496 CACHE CONTROLLER User Manual

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HARDWARE INTERFACE
5.2.2.39. CPWT
CPWT
latched Pentium processor PWT pin
A latched version of the Pentium processor PWT output signal.
Output from 82496 Cache Controller (pin K01)
Synchronous to ClK
Signal Description
CPWT reflects the Pentium processor PWT output signal during a CPU cycle on the memory
bus. CPWT is inactive (LOW) during write-backs, snoop write-backs, and allocations. Write
cycles with PWT active are not allocatable.
CPWT can be used, along with CPCD, to distinguish between write hit to [S] state and write
miss cycles. In all cases PALLC# will be inactive (high). See Table 5-3.
When Driven
CPWT is valid from the CLK ofCADS# and SNPADS# until the CLK ofCRDY# or CNA#.
Relation to Other Signals
Pin Symbol
Relation to Other Signals
CADS# Address and cycle specification signals (Le., APIC#, CCACHE#, CD/C#, CMIIO#,
CPCD, CPWT, CSCYC, CW/R#, CWAY, KlOCK#, MAP, MBT[3:0J, MCACHE#,
MCFA, MSET, MTAG, NENE#, PAllC#, RDYSRC, and SMlN#) are valid with
CADS#.
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