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Intel 82562EZ Design Manual

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82562EZ(EX)/82547GI(EI) Dual
Footprint
Design Guide
Networking Silicon
317520-002
Revision 2.2

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Summary of Contents for Intel 82562EZ

  • Page 1 82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide Networking Silicon 317520-002 Revision 2.2...
  • Page 2 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right.
  • Page 3 Updated reference schematics to reflect current differential pair termination resistor values for the 82547GI/EI. Updated section 4.2.1 “Termination Resistors for Designs Based on 82562EZ/ EX PLC Device” to reflect current resistor and RBIAS values. Updated section 4.3.1 “Termination Resistors for Designs Based on 8257GI(EI) Gigabit Ethernet Controller”...
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  • Page 5: Table Of Contents

    Reference Documents ........................2 Product Codes ..........................2 System Data Port Interfaces ....................3 LCI Connection to 82562EZ(EX) Platform LAN Connect Device ..........3 CSA Port Connection to 82547GI(EI) Gigabit Ethernet Controller ..........4 2.2.1 Generation/Distribution of Reference Voltages ............... 4 2.2.2...
  • Page 6 Trace Routing ..........................23 Ground Plane Separation ......................26 Ideal Ground Split Implementation ..................... 27 Termination Plane Example for 82562EZ(EX) PLC Device and Discrete Magnetics ....28 82562EZ(EX) PLC Device Differential Signal Termination............29 Indirect Probing Setup ........................ 52 Direct Probing Method ........................ 55...
  • Page 7 CSA Port Reference Circuit Specifications................... 4 CSA Port CI_RCOMP Resistor Values..................5 Crystal Parameters ........................7 82547GI(EI) Recommended Crystals...................8 82562EZ(EX) Memory Layout (128 Byte EEPROM) ..............13 82562EZ(EX) Memory Layout (512 Byte EEPROM) ..............14 82562EZ(EX) Recommended Magnetics Modules..............14 Microwire 64 x 16 Serial EEPROMs ...................16 SPI Serial EEPROMs for 82547GI(EI) Controller ...............16...
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  • Page 9: Introduction

    Intel 865 Chipset and Intel 875 Chipset. The document identifies similarities and differences between the 82562EZ(EX) Platform LAN Connect device and the 82547GI(EI) Gigabit Ethernet Controller. Section 2 describes the port interfaces specific to each device. Section 3 explains what you need to know to hook up an Ethernet device to the system.

  • Page 10: Reference Documents

    IEEE Standard 802.3, 2000 Edition. Incorporates various IEEE standards previously published separately. • I/O Control Hub 2, 3, and 4 EEPROM Map and Programming Information. Intel Corporation. • I/O Control Hub 5, 6, and 7 EEPROM Map and Programming Information. Intel Corporation.

  • Page 11: System Data Port Interfaces

    Line termination mechanisms are not specified for the LCI. Slew rate controlled output buffers achieve acceptable signal integrity by controlling signal reflection, undershoot and ringing. For details about how to connect the LCI interface between the 82562EZ(EX) Platform LAN Connect device and ICH5, please refer to the 82562ET/EM Platform LAN Connect Printed Circuit ®...

  • Page 12: Csa Port Connection To 82547Gi(Ei) Gigabit Ethernet Controller

    The CSA interface uses IGTL buffers to achieve very high data speeds while controlling transmission line characteristics. For details on connecting the CSA interface between the ® 82547GI(EI) Gigabit Ethernet Controller and the MCH, please refer to the Intel 865 Chipset ®...

  • Page 13: Csa Port Resistive Compensation

    82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide The values of R1, R2 and R3 must be rated at ±1% tolerance. The selected resistor values must also ensure that the reference voltage and reference swing voltage tolerance are maintained over the input leakage specification. A 0.1 µF capacitor (C1 in Figure 2) should be placed within 0.5 inches...
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  • Page 15: Ethernet Component Design Guidelines

    Ethernet Component Design Guidelines These sections provide recommendations for selecting components and connecting special pins. The main design elements are the 82562EZ(EX) Platform LAN Connect device or the 82547GI(EI) Gigabit Ethernet Controller, an integrated magnetics module with RJ-45 connector, and a crystal clock source.

  • Page 16: 82547Gi(Ei) Recommended Crystals

    3.1.1.2 Nominal Frequency Intel® Ethernet controllers use a crystal frequency of 25.000 MHz. The 25 MHz input is used to generate a 125 MHz transmit clock for 100BASE-TX and 1000BASE-TX operation; 10 MHz and 20 MHz transmit clocks, for 10BASE-T operation.

  • Page 17: Crystal Circuit

    The formula for crystal load capacitance is as follows: ⋅ C1 C2 ------------------------- stray where C1 = C2 = 22 pF (as suggested in most Intel reference designs) and C = allowance for additional capacitance in pads, traces and the chip carrier stray within the Ethernet controller package An allowance of 3 pF to 7 pF accounts for lumped stray capacitance.

  • Page 18: Reference Crystal

    AT strips, rather than circular AT quartz blanks. Some crystal data sheets list crystals with a maximum drive level of 1 mW. However, Intel® Ethernet controllers drive crystals to a level less than the suggested 0.5 mW value. This parameter does not have much value for on-chip oscillator use.

  • Page 19: Reference Crystal Selection

    CLoad capacitance. Note: For 82547GI(EI) devices, Intel® recommends choosing a crystal with a ESR value of 10 Ω or less, an equivalent Cload of 18 pF, and a maximum of 30 ppm frequency shift. Cload is defined to be the load capacitance of the crystal, specified by the crystal vendor.

  • Page 20: Integrated Magnetics Module

    Magnetics modules for 1000BASE-T Ethernet are similar to those designed solely for 10/100 Mbps, with the exception of four differential signal pairs instead of two for 10/100 Mbps. Designing with the 82562EZ(EX) Platform LAN Connect Device This section provides design guidelines specific to the PLC device.

  • Page 21: Serial Eeprom For 82562Ez(Ex) Implementations

    Isolate Mode. 3.2.2 Serial EEPROM for 82562EZ(EX) Implementations Serial EEPROM for LAN implementations based on 82562EZ(EX) devices connects to the ICH5. Depending upon the size of the EEPROM, the 82562EZ(EX) may or may not support legacy manageability. Table 7 Table 8 list the EEPROM map for the 82562EZ(EX) PLC device.

  • Page 22: Magnetics Modules For 82562Ez(Ex) Plc Device

    3.2.4 Power Supplies for 82562EZ(EX) PLC Implementations The 82562EZ(EX) PLC device uses a single 3.3 V power supply. The 3.3 V supply must provide approximately 90 mA current for full speed operation. Standby power must be furnished in order to wake up from powerdown.

  • Page 23: Serial Eeprom For 82547Gi(Ei) Controller Implementations

    5. The device is in a low power state – equivalent to D3 w/ no wake or manageability. Note: To use this configuration for the 82562EZ(EX) Platform LAN Connect device, be sure the AND gate U1 is populated. Depopulate the 0 Ω resistor R2.

  • Page 24: Microwire 64 X 16 Serial Eeproms

    93C66 Microwire or AT25040 SPI* Serial EEPROM. ASF 2.0 requires an 8K SPI* Serial EEPROM. Intel has an MS-DOS* software utility called EEUPDATE, which can be used to program EEPROM images in development or production line environments. To obtain a copy of this program, contact your Intel representative.

  • Page 25: Eeprom Map Information

    82547GI(EI) device. These modules also contain integrated USB jacks. A good quality Gigabit Ethernet controller can also be used with the 82562EZ(EX) PLC device. Note: These components are pin-compatible with the magnetics modules shown in...

  • Page 26: 82547Gi(Ei) Controller Power Supply Filtering

    82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide Instead of using external regulators to supply 1.2 V and 1.8 V, the designer can use power transistors in conjunction with on-chip regulation circuitry. See the reference schematic for an implementation example. The 82547GI(EI) controller has a LAN_PWR_GOOD input. Treat this signal as an external device reset which works in conjunction with the internal power-on reset circuitry.

  • Page 27: 82547Gi(Ei) Device Test Capability

    A BSDL (Boundary Scan Definition Language) file describing the 82547GI(EI) device is available for use in your test environment. The controller also contains an XOR test tree mechanism for simple board tests. Details of XOR tree operation may be obtained through your Intel representative.
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  • Page 29: Ethernet Component Layout Guidelines

    82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide Ethernet Component Layout Guidelines These sections provide recommendations for performing printed circuit board layouts. Good layout practices are essential to meet IEEE PHY conformance specifications and EMI regulatory requirements. General Layout Considerations for Ethernet Controllers Critical signal traces should be kept as short as possible to decrease the likelihood of being affected by high frequency noise from other signals, including noise carried on power and ground planes.

  • Page 30: Crystals

    82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide Integrated RJ-45 Keep silicon traces at least 1 inch from edge of PCB (2 inches preferred) w/LAN Magnetics Keep LAN silicon 1 to 4 inches from LAN connector Keep 100 mil minimum distance between TX...

  • Page 31: Differential Pair Trace Routing

    82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide • Layer 3 is used for power planes. • Layer 4 is a signal layer. For Gigabit designs, it is common to route two of the differential pairs on this layer. This board stack up configuration can be adjusted to conform to your company's design rules.

  • Page 32: Signal Trace Geometry

    82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide • The reference plane for the differential pairs should be continuous and low impedance. It is recommended that the reference plane be either ground or 1.8 V (the voltage used by the PHY). This provides an adequate return path for and high frequency noise currents.

  • Page 33: Impedance Discontinuities

    82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide 4.1.7 Impedance Discontinuities Impedance discontinuities cause unwanted signal reflections. Avoid vias (signal through holes) and other transmission line irregularities. If vias must be used, a reasonable budget is two per differential trace. Unused pads and stub traces should also be avoided.

  • Page 34: Traces For Decoupling Capacitors

    82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide The following guidelines help reduce circuit inductance in both backplanes and motherboards: • Route traces over a continuous plane with no interruptions. Do not route over a split power or ground plane. If there are vacant areas on a ground or power plane, avoid routing signals over the vacant area.

  • Page 35: Ideal Ground Split Implementation

    82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide Figure 8 below shows the preferred method for implementing a ground split under an integrated magnetics module/RJ-45 connector. The capacitor stuffing options (C1 – C6) are used to reduce/ filter high frequency emissions. The value(s) of the capacitor stuffing options may be different for each board.

  • Page 36: Special Considerations For Non-Integrated Magnetics Modules And Rj-45 Connectors

    Transient) testing. If a discrete capacitor is used, to meet the EFT requirements it should be rated for at least 1000 Vac. RJ-45 Magnetics module Termination plane Additional capacitance that may be required for EFT testing LAN_term_plane Figure 9. Termination Plane Example for 82562EZ(EX) PLC Device and Discrete Magnetics...

  • Page 37: Layout For The 82562Ez(Ex) Platform Lan Connect Device

    Light Emitting Diodes for Designs Based on 82562EZ(EX) PLC Device The 82562EZ(EX) PLC device has three high-current outputs to directly drive LEDs for link, activity and speed indication. Since LEDs are likely to be integral to a magnetics module, take care to route the LED traces away from potential sources of EMI noise.

  • Page 38: Layout For The 82547Gi(Ei) Gigabit Ethernet Controller

    82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide Layout for the 82547GI(EI) Gigabit Ethernet Controller 4.3.1 Termination Resistors for Designs Based on 82547GI(EI) Gigabit Ethernet Controller The four differential pairs are terminated with 49.9 Ω (1% tolerance) resistors, placed near the 82547GI(EI) controller. One resistor connects to the MDI+ signal trace and another resistor connects to the MDI- signal trace.

  • Page 39: Troubleshooting Common Physical Layout Issues

    5 Ω to 20 Ω. Short traces will have fewer problems if the differential impedance is slightly off target. 9. For 82562EZ(EX) PLC designs, use of capacitor that is too large between the transmit traces and/or too much capacitance on the magnetic module's transmit center tap to ground. Using capacitors more than a few pF in either of these locations can slow the 100 Mbps rise and fall time.
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  • Page 41: Design And Layout Checklists

    82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide Design and Layout Checklists The Design and Layout checklists are in Portable Data Format (PDF) and available to aid designers via: http://developer.intel.com.
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  • Page 43: Ball Number To Signal Mapping With Population Options

    Section 7.0. The schematic names follow conventions used by Intel design engineers on their design tools. Table 14. Ball Number to Signal Mapping (Sheet 1 of 7) Ball...
  • Page 44 82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide Table 14. Ball Number to Signal Mapping (Sheet 2 of 7) (Continued) Ball 82562EZ(EX) 82547GI(EI) Pin Signal Name 82562EZ(EX) Pop Option Comment Pin Name Name Difference? Connection? Required? SPDLED# LED2/LINK100# Same signal different name TOUT...
  • Page 45 82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide Table 14. Ball Number to Signal Mapping (Sheet 3 of 7) (Continued) Ball 82562EZ(EX) 82547GI(EI) Pin Signal Name 82562EZ(EX) Pop Option Comment Pin Name Name Difference? Connection? Required? ISOL_EXEC 82562EZ: No Connect. Internal Pull-Down. 82547GI(EI): No Connect.
  • Page 46 82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide Table 14. Ball Number to Signal Mapping (Sheet 4 of 7) (Continued) Ball 82562EZ(EX) 82547GI(EI) Pin Signal Name 82562EZ(EX) Pop Option Comment Pin Name Name Difference? Connection? Required? MDI[2]+ MDI[2]- CI_CLK CI[9] CSA_1.2V VCCR 1.2 V 3.3 V / 1.2 V Plane...
  • Page 47 82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide Table 14. Ball Number to Signal Mapping (Sheet 5 of 7) (Continued) Ball 82562EZ(EX) 82547GI(EI) Pin Signal Name 82562EZ(EX) Pop Option Comment Pin Name Name Difference? Connection? Required? CI[1] CI[2] CSA_1.2V VCCR 1.2 V 3.3 V / 1.2 V Plane 1.2 V...
  • Page 48 82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide Table 14. Ball Number to Signal Mapping (Sheet 6 of 7) (Continued) Ball 82562EZ(EX) 82547GI(EI) Pin Signal Name 82562EZ(EX) Pop Option Comment Pin Name Name Difference? Connection? Required? ADV10 82562EZ: No Connect. Internal Pull-Down. 82547GI(EI): No Connect.
  • Page 49 82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide Table 14. Ball Number to Signal Mapping (Sheet 7 of 7) (Continued) Ball 82562EZ(EX) 82547GI(EI) Pin Signal Name 82562EZ(EX) Pop Option Comment Pin Name Name Difference? Connection? Required? CI[7] CI_RCOMP CI_VREF 1.2 V 3.3 V 3.3 V...
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  • Page 51: Dual Footprint Reference Schematic

    82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide Dual Footprint Reference Schematic The following pages illustrate a dual purpose 10/100 and 10/100/1000 design using the 82562EZ(EX) Platform LAN Connect device and the 82547GI(EI) Gigabit Ethernet Controller.
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  • Page 59: Measuring Lan Reference Frequency Using A Frequency Counter

    ±50 parts per million (ppm). Note: Intel recommends a frequency tolerance of ±30 (ppm). Most Intel LAN devices will operate properly with a 25.000 MHz reference crystal, provided it meets the recommended requirements for frequency stability, equivalent series resistance at resonance (ESR), and load capacitance.

  • Page 60: Indirect Probing Setup

    Almost all Intel LAN silicon that support 1000BASE-T Ethernet can provide a buffered 125 MHz clock, which can be used for indirect probing of the transmitter reference clock. The buffered 125 MHz clock will be a 5X multiple of the crystal circuit’s reference frequency...
  • Page 61 82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide Indirect Frequency Measurement and Frequency Accuracy Calculation Steps 1. Make sure the system BIOS has the LAN controller enabled. 2. Connect the test equipment as shown in Figure 3. Using the appropriate controls for your model of high resolution digital counter, make sure it can display ~125.0000 MHz with at least four decimal places frequency resolution.
  • Page 62 82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide Example 2. Given: The measured averaged center frequency is 125.00087 MHz (or 125,000,870 Hertz). 125000870 125000000 – FrequencyAccuracy ppm ---------------------------------------------------------------- 6.96ppm ⁄ 125000000 1000000 Note: The following items should be noted for an ideal reference crystal on a typical printed circuit board.

  • Page 63: Direct Probing Method

    82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide Figure 12. Direct Probing Method Direct Frequency Measurement and Frequency Accuracy Calculation Steps 1. Make sure the system BIOS has the LAN controller enabled. 2. Connect the test equipment as shown in Figure 3. Using the appropriate controls for your model of high resolution digital counter, make sure it can display ~25.0000 MHz with at least four decimal places frequency resolution.
  • Page 64 82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide – FrequencyAccuracy ppm ------------------------------- - ⁄ y 1000000 where x = Average measured frequency in Hertz and y = Ideal reference frequency in Hertz Example 3. Given: The measured averaged center frequency is 24.99963 MHz (or 24,999,630 Hertz).

  • Page 65: B Gigconf.exe Register Settings For 82547Gi(Ei) Devices

    1. Boot to DOS using a DOS Boot Diskette. 2. Launch Gigconf from the diskette (gigconf.exe). 3. Select the Intel network connection to be measured. a. If multiple adapters are installed, use the arrow keys to navigate to highlight the selected adapter and press Enter.
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