Flush - Intel 82496 CACHE CONTROLLER User Manual

HARDWARE INTERFACE
5.2.2.51. FLUSH#
FLUSH# Cache Flush
Causes a Pentium processor and/or 82496 Cache Controller cache flush.
Input to 82496 Cache Controller (pin P05), and Pentium processor (pin U02)
Asynchronous
82496 Cache Controller internal Pull-up
Signal Description
82496 Cache Controller FLUSH# invalidates the entire 82496 Cache Controller and Pentium
processor tag arrays. Two clocks are required to lookup a tag entry if the result is a miss. The
82496 Cache Controller also invalidates tags in the CPU cache by executing inquire and back-
invalidation cycles to the Pentium processor. All modified first and second-level cache lines
will be written to memory.
There are two reasons for potentially wanting to assert the CPU FLUSH# in addition to the
82496 Cache Controller FLUSH#. One, if the MBC wants to see the processor flush
acknowledge special cycle, and two, to assure that no Pentium processor cache hits are
occurring once FLUSH# has been asserted to the 82496 Cache Controller. This is because the
82496 Cache Controller flush operation does not inhibit Pentium processor cache hit
operations. For optimum performance, issue FLUSH# to only the 82496 Cache Controller.
When the MBC decodes a Pentium processor Flush (due to the INVD or WBINVD
instructions) or Write Back (due to the WBINVD instruction) special cycle, it must provide
FLUSH# to the 82496 Cache Controller. The 82496 Cache Controller/82491 Cache SRAM
treats Flush and Write Back special cycles like I/O cycles. They are not posted, and the MBC
must provide BRDY#. The WBINVD instruction causes the Pentium processor to issue the
Flush special cycle followed by the Write Back special cycle.
The 82496 Cache Controller/82491 Cache SRAM second-level cache can be snooped during
the flush operation. The snooping protocols are the same as with any memory bus cycle.
When Sampled
FLUSH# can be asserted at any time. The 82496 Cache Controller completes all outstanding
transactions on the CPU and memory bus before beginning the flush operation (namely, all
BRDY#s and CRDY#s have been provided for outstanding memory bus cycles). The memory
bus controller does not have to prevent flushing during locked cycles because the 82496 Cache
Controller completes locked transactions before the flush begins.
Once a flush has begun (FSIOUT# active), FLUSH# is ignored until the operation completes.
If RESET is activated while the flush is in progress, the flush is aborted and RESET is
executed immediately.
FLUSH# is an asynchronous input. FLUSH# must have a pulse width of at least two CLKs to
ensure recognition by the 82496 Cache Controller.
I 5-95