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Intel 80C186EA Preliminary Information

16-bit high-integration embedded processors
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80C186EA 80C188EA AND 80L186EA 80L188EA
16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS
Integrated Feature Set
Y
Static 186 CPU Core
Power Save Idle and Powerdown
Modes
Clock Generator
2 Independent DMA Channels
3 Programmable 16-Bit Timers
Dynamic RAM Refresh Control Unit
Programmable Memory and
Peripheral Chip Select Logic
Programmable Wait State Generator
Local Bus Controller
System-Level Testing Support
(High Impedance Test Mode)
Speed Versions Available (5V)
Y
25 MHz (80C186EA25 80C188EA25)
20 MHz (80C186EA20 80C188EA20)
13 MHz (80C186EA13 80C188EA13)
The 80C186EA is a CHMOS high integration embedded microprocessor The 80C186EA includes all of the
features of an ''Enhanced Mode'' 80C186 while adding the additional capabilities of Idle and Powerdown
Modes In Numerics Mode the 80C186EA interfaces directly with an 80C187 Numerics Coprocessor
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT
80C186 Upgrade for Power Critical Applications
Y
Fully Static Operation
Y
True CMOS Inputs and Outputs
Y
October 1995
INTEL CORPORATION 1995
Speed Versions Available (3V)
Y
13 MHz (80L186EA13 80L188EA13)
8 MHz (80L186EA8 80L188EA8)
Direct Addressing Capability to
Y
1 Mbyte Memory and 64 Kbyte I O
Supports 80C187 Numeric Coprocessor
Y
Interface (80C186EA only)
Available in the Following Packages
Y
68-Pin Plastic Leaded Chip Carrier
(PLCC)
80-Pin EIAJ Quad Flat Pack (QFP)
80-Pin Shrink Quad Flat Pack (SQFP)
Available in Extended Temperature
Y
Range (
40 C to
b
a
85 C)
272432 –1
Order Number 272432-003
1

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  Summary of Contents for Intel 80C186EA

  • Page 1 Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make...
  • Page 2: Table Of Contents

    80C186EA 80C188EA 80L186EA 80L188EA 80C186EA 80C188EA AND 80L186EA 80L188EA 16-Bit High Integration Embedded Processor CONTENTS INTRODUCTION 80C186EA CORE ARCHITECTURE Bus Interface Unit Clock Generator 80C186EA PERIPHERAL ARCHITECTURE Interrupt Control Unit Timer Counter Unit DMA Control Unit Chip-Select Unit Refresh Control Unit...
  • Page 3 80C186EA 80C188EA 80L186EA 80L188EA NOTE Pin names in parentheses apply to the 80C186EA 80L188EA Figure 1 80C186EA 80C188EA Block Diagram...
  • Page 4: Introduction

    Physi- cally and functionally the ‘‘C’’ and ‘‘L’’ devices are identical The 80C186EA is the second product in a new gen- eration of low-power high-integration microproces- sors It enhances the existing 80C186XL family by...
  • Page 5: 80C186Ea Peripheral Architecture

    (B) Clock Connection Figure 2 Clock Configurations Interrupt Control Unit The 80C186EA can receive interrupts from a num- ber of sources both internal and external The Inter- rupt Control Unit (ICU) serves to merge these re- quests on a priority basis for individual service by...
  • Page 6 80C186EA 80C188EA 80L186EA 80L188EA Function Offset Offset Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Timer 0 Count Reserved 52H Timer 0 Compare A Reserved 54H Timer 0 Compare B Reserved Timer 0 Control Reserved Timer 1 Count Reserved...
  • Page 7: Dma Control Unit

    Figure 4 80C186EA Slave Mode Peripheral Control Block Registers DMA Control Unit The 80C186EA DMA Contol Unit provides two inde- pendent high-speed DMA channels Data transfers can occur between memory and I O space in any combination memory to memory memory to I O...
  • Page 8: 80C187 Interface (80C186Ea Only)

    80L186EA ONCE Test Mode To facilitate testing and inspection of devices when fixed into a target system the 80C186EA has a test mode available which forces all output and input output pins to be placed in the high-impedance state ONCE stands for ‘‘ON Circuit Emulation’’ The...
  • Page 9: Package Information

    PACKAGE INFORMATION This section describes the pins pinouts and thermal characteristics for the 80C186EA in the Plastic Leaded Chip Carrier (PLCC) package Shrink Quad Flat Pack (SQFP) and Quad Flat Pack (QFP) pack- age For complete package specifications and infor-...
  • Page 10 80C186EA 80C188EA 80L186EA 80L188EA Table 2 Pin Description Nomenclature Symbol S(E) S(L) A(E) A(L) H(1) H(0) H(Z) H(Q) H(X) R(WH) R(1) R(0) R(Z) R(Q) R(X) I(1) I(0) I(Z) I(Q) I(X) P(1) P(0) P(Z) P(Q) P(X) Description Power Pin (Apply Voltage)
  • Page 11 CPU NMI is latched internally TEST BUSY is sampled upon reset to determine whether the 80C186EA is to enter Numerics Mode In regular operation the pin is TEST TEST is used during the execution of the WAIT...
  • Page 12 Byte High Enable output to indicate that the bus cycle in progress is transferring data over the upper half of the data bus BHE and A0 have the following logical encoding Encoding (For 80C186EA 80L186EA Only) Word Transfer Even Byte Transfer...
  • Page 13: Ac Characteristics 80C186Ea20

    P(1) NOTE Pin names in parentheses apply to the 80C188EA and 80L188EA 80C186EA 80C188EA 80L186EA 80L188EA Description WRite output signals that data available on the data bus are to be written into the accessed memory or I O device In Queue Status...
  • Page 14 Select outputs which will go active whenever the address P(1) of a memory bus cycle is within the address limitations programmed by the user In Numerics Mode (80C186EA only) three of the pins become handshaking pins for the 80C187 The CoProcessor REQuest input signals that a...
  • Page 15: 80C186Ea Pinout

    80C186EA PINOUT Tables 4 and 5 list the 80C186EA pin names with package location for the 68-pin Plastic Leaded Chip Carrier (PLCC) component Figure 9 depicts the complete 80C186EA 80L186EA pinout (PLCC pack- age) as viewed from the top side of the component...
  • Page 16 Pin names in parentheses apply to the 80C186EA 80L188EA NOTES 1 The nine-character alphanumeric code (XXXXXXXXD) underneath the product number is the Intel FPO number 2 Pin names in parentheses apply to the 80C186EA 80L188EA Figure 5 68-Lead PLCC Pinout Diagram...
  • Page 17 LOCK AD12 (A12) HOLD AD13 (A13) HLDA AD14 (A14) AD15 (A15) Power Name A19 S6 NOTE Pin names in parentheses apply to the 80C186EA 80L188EA 80C186EA 80C188EA 80L186EA 80L188EA Processor Control Location Name Location RESIN RESOUT CLKIN OSCOUT CLKOUT TEST BUSY...
  • Page 18 Pin names in parentheses apply to the 80C186EA 80L188EA NOTES 1 The nine-character alphanumeric code (XXXXXXXXD) underneath the product number is the Intel FPO number 2 Pin names in parentheses apply to the 80C186EA 80L188EA Figure 6 Quad Flat Pack (EIAJ) Pinout Diagram...
  • Page 19 AD15 (A15) No Connection A16 S3 A17 S4 A18 S5 A19 S6 NOTE Pin names in parentheses apply to the 80C186EA 80L188EA Table 9 SQFP Pin Locations with Pin Names AD8 (A8) AD9 (A9) AD10 (A10) AD11 (A11) AD12 (A12)
  • Page 20: Package Thermal Specifications

    2 Pin names in parentheses apply to the 80C188EA PACKAGE THERMAL SPECIFICATIONS The 80C186EA 80L186EA is specified for operation when T (the case temperature) is within the range of 0 C to 85 C (PLCC package) or 0 C to 106 C...
  • Page 21: Electrical Specifications

    0 5V to V Recommended Connections Power and ground connections must be made to multiple V and V pins Every 80C186EA based circuit board should contain separate power (V and ground (V ) planes All V and V be connected to the appropriate plane Pins identi- fied as ‘‘N C ’’...
  • Page 22: Dc Specifications

    80C186EA 80C188EA 80L186EA 80L188EA DC SPECIFICATIONS (80C186EA 80C188EA) Symbol Parameter Supply Voltage Input Low Voltage for All Pins Input High Voltage for All Pins Output Low Voltage Output High Voltage Input Hysterisis on RESIN Input Leakage Current (except RD QSMD UCS LCS MCS0 PEREQ...
  • Page 23 2 Output pins are floated using HOLD or ONCE Mode 3 Measured at worst case temperature and V device in RESET (RESIN held low) 4 Output capacitance is the capacitive load of a floating output pin 80C186EA 80C188EA 80L186EA 80L188EA 0 3 V 0 7 V 0 45...
  • Page 24: Icc Versus Frequency And Voltage

    Device operating voltage (V Device capacitance Device operating frequency Device current Measuring C on a device like the 80C186EA would be difficult Instead C is calculated using the above formula by measuring I at a known V and frequency (see Table 11) Using this C...
  • Page 25: Ac Specifications

    NCS INTA1 0 S2 0 RD WR BHE (RFSH) DT R CHOF LOCK S2 0 A19 16 DEN AD15 0 (A15 8 AD7 0) CLOF 80C186EA 80C188EA 80L186EA 80L188EA (12) 25 MHz 20 MHz 38 5 (T 2) (T 2)
  • Page 26 80C186EA 80C188EA 80L186EA 80L188EA AC SPECIFICATIONS (Continued) AC Characteristics 80C186EA25 80C186EA20 80C186EA13 Symbol Parameter SYNCHRONOUS INPUTS TEST NMI INT3 0 CHIS T1 0IN ARDY TEST NMI INT3 0 CHIH T1 0IN ARDY AD15 0 (AD7 0) ARDY CLIS SRDY DRQ1 0...
  • Page 27: Ac Characteristics 80L186Ea13

    10 Setup and Hold are required for proper operation 11 T applies to BHE (RFSH) and A19 16 only after a HOLD release CHOVS 12 Pin names in parentheses apply to the 80C188EA 80L188EA 80C186EA 80C188EA 80L186EA 80L188EA 13 MHz 8 MHz 38 5 62 5...
  • Page 28 80C186EA 80C188EA 80L186EA 80L188EA AC SPECIFICATIONS AC Characteristics 80L186EA13 80L186EA8 Symbol Parameter SYNCHRONOUS INPUTS TEST NMI INT3 0 T1 0IN ARDY CHIS TEST NMI INT3 0 T1 0IN ARDY CHIH AD15 0 (AD7 0) ARDY SRDY DRQ1 0 CLIS AD15 0 (AD7 0) ARDY SRDY DRQ1 0...
  • Page 29: Relative Timings

    4 Not applicable to latched A2 1 These signals change only on falling T 5 For write cycle followed by read cycle 6 Operating conditions for 25 MHz are 0 C to 80C186EA 80C188EA 80L186EA 80L188EA (2 T) (2 T)
  • Page 30: Ac Test Conditions

    80C186EA 80C188EA 80L186EA 80L188EA AC TEST CONDITIONS The AC specifications are tested with the 50 pF load shown in Figure 8 See the Derating Curves section to see how timings vary with load capacitance 272432 – 8 50 pF for all signals...
  • Page 31 NOTE 20% V Float 80% V CC k Figure 10 Output Delay and Float Waveform NOTE RESIN measured to CLKIN not CLKOUT Figure 11 Input Setup and Hold 80C186EA 80C188EA 80L186EA 80L188EA 272432 –10 272432 –11...
  • Page 32 80C186EA 80C188EA 80L186EA 80L188EA NOTES for write cycle followed by read cycle DXDL 2 Pin names in parentheses apply to tthe 80C188EA Figure 12 Relative Signal Waveform 272432 –12...
  • Page 33: Derating Curves

    The RESIN pin is designed to operate cor- rectly using an RC reset circuit but the designer 80C186EA 80C188EA 80L186EA 80L188EA 272432– 13 Figure 14 Typical Rise and Fall Variations Versus Load Capacitance...
  • Page 34 80C186EA 80C188EA 80L186EA 80L188EA Figure 15 Powerup Reset Waveforms...
  • Page 35 80C186EA 80C188EA 80L186EA 80L188EA Figure 16 Warm Reset Waveforms...
  • Page 36: Bus Cycle Waveforms

    80C186EA 80C188EA 80L186EA 80L188EA BUS CYCLE WAVEFORMS Figures 17 through 23 present the various bus cycles that are generated by the processor What is shown in the figure is the relationship of the various bus signals to CLKOUT These figures along with the information...
  • Page 37 80C186EA 80C188EA 80L186EA 80L188EA 272432-18 NOTES 1 During the data phase of the bus cycle A19 S6 is driven high for a DMA cycle 2 Pin names in parentheses apply to the 80C188EA Figure 18 Write Cycle Waveform...
  • Page 38 80C186EA 80C188EA 80L186EA 80L188EA NOTES 1 The processor drives these pins to 0 during Idle and Powerdown Modes 2 Pin names in parentheses apply to the 80C188EA Figure 19 Halt Cycle Waveform 272432 –19...
  • Page 39 80C186EA 80C188EA 80L186EA 80L188EA NOTES 272432 –20 1 INTA occurs one clock later in Slave Mode 2 Pin names in parentheses apply to the 80C188EA Figure 20 INTA Cycle Waveform...
  • Page 40 80C186EA 80C188EA 80L186EA 80L188EA NOTE 1 Pin names in parentheses apply to the 80C188EA Figure 21 HOLD HLDA Waveform 272432 –21...
  • Page 41 80C186EA 80C188EA 80L186EA 80L188EA 272432 –22 NOTE 1 Pin names in parentheses apply to the 80C188EA Figure 22 DRAM Refresh Cycle During Hold Acknowledge...
  • Page 42 80C186EA 80C188EA 80L186EA 80L188EA NOTES 1 Generalized diagram for READ or WRITE 2 ARDY low by either edge causes a wait state Only rising ARDY is fully synchronized 3 SRDY low causes a wait state SRDY must meet setup and hold times to ensure correct device operation...
  • Page 43: Execution Timings

    (BIU) and exe- cution unit With a 16-bit BIU the 80C186EA has sufficient bus performance to endure that an adequate number of prefetched bytes will reside in the queue (6 bytes)
  • Page 44: Instruction Set Summary

    80C186EA 80C188EA 80L186EA 80L188EA INSTRUCTION SET SUMMARY Function DATA TRANSFER Move Register to Register Memory 1 0 0 0 1 0 0 w Register memory to register 1 0 0 0 1 0 1 w Immediate to register memory 1 1 0 0 0 1 1 w...
  • Page 45 Memory-Word Shaded areas indicate instructions not available in 8086 8088 microsystems NOTE Clock cycles shown for byte transfers For word operations add 4 clock cycles for all memory transfers 80C186EA 80C188EA 80L186EA 80L188EA (Continued) Format mod reg r m mod 0 0 0 r m...
  • Page 46 80C186EA 80C188EA 80L186EA 80L188EA INSTRUCTION SET SUMMARY Function ARITHMETIC (Continued) IMUL Integer multiply (signed) 1 1 1 1 0 1 1 w Register-Byte Register-Word Memory-Byte Memory-Word IMUL Integer Immediate multiply 0 1 1 0 1 0 s 1 (signed) Divide (unsigned)
  • Page 47 1 1 1 1 1 1 1 1 Shaded areas indicate instructions not available in 8086 8088 microsystems NOTE Clock cycles shown for byte transfers For word operations add 4 clock cycles for all memory transfers 80C186EA 80C188EA 80L186EA 80L188EA (Continued) Format mod reg r m...
  • Page 48 80C186EA 80C188EA 80L186EA 80L188EA INSTRUCTION SET SUMMARY Function CONTROL TRANSFER (Continued) Return from CALL Within segment 1 1 0 0 0 0 1 1 Within seg adding immed to SP 1 1 0 0 0 0 1 0 Intersegment 1 1 0 0 1 0 1 1...
  • Page 49 EA calculation time is 4 clock cycles for all modes and is included in the execution times given whenev- er appropriate Segment Override Prefix 0 0 1 reg 1 1 0 80C186EA 80C188EA 80L186EA 80L188EA (Continued) Format reg is assigned according to the following DISP...
  • Page 50: Revision History

    272307-001 SB80C186EA SB80L186EA 272308-001 SB80C188EA SB80L188EA ERRATA An 80C186EA 80L186EA with a STEPID value of 01H or 02H has the following known errata A device with a STEPID of 01H or 02H can be visually identi- fied by noting the presence of an ‘‘A’’ ‘‘B’’ or ‘‘C’’...

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