Mx4/8 - Intel 82496 CACHE CONTROLLER User Manual

PINOUTS
Table 1-10. Pentium™ Processor CPU-Cache Chip Set Brief Pin Descriptions (Contd.)
Symbol Type Part Name and Function
MTHIT#
0
CC Memory Bus Tag Hit is driven by the 82496 Cache Controller during
snoop cycles to indicate whether a snooping address hits an exclusive,
shared, or modified cache line. MTHIT# is valid in the ClK following
SNPCYC# and remains valid until the ClK of the next SNPCYC#.
MTR4/8# I CS The Memory Transfer Configuration signal is sampled at the falling
edge of RESET and determines the number of transfers needed on the
memory bus for each cache line. If MTR4/8# is high, there are four
transfers for each cache line; If MTR4/8# is low, there are eight transfers.
MTR4/8# shares a pin with the 82491 Cache SRAM input signal MSEl#.
MWBIWT# I CC Memory Bus Write Policy allows the memory bus to dynamically indicate
to the 82496 Cache Controller whether the write policy is write-through or
write-back. MWBIWT# is sampled when SWEND# becomes active. If
MWBIWT# is sampled low, the tag state changes to shared (used, for
example, when the line is detected in another cache). If MWBIWT# is
sampled high, the tag state can change to an exclusive state.
MX4/8# I
CS
On the falling edge of RESET, the Memory I/O Bits Configuration signal
is sampled to determine the number of I/O pins to be used for the memory
bus. If MX4/8# is HIGH, four I/O pins are used. If MX4/8# is lOW, eight
I/O pins are used.
MX4/8# shares a pin with the 82491 Cache SRAM input signal MZBT#.
MZBT# I CS When sampled active with MSEl# inactive or MEOC# active, Memory
Zero Based Transfer indicates that burst location zero of the memory bus
cycle should be the starting sub-line address independent of the sub-line
address requested by the Pentium processor.
MZBT# shares a pin with the Configuration signal MX4/B#.
NA# 0
CC
An active Next Address signal indicates that the 82496 Cache Controller
I P is ready to accept a new bus cycle although all data transfers for the
current cycle have not yet completed. The Pentium processor will drive out
a pending cycle two clocks after NA# is asserted. The Pentium processor
supports up to 2 outstanding bus cycles.
NENE# 0 CC Next Near allows the memory bus controller (MBC) to take advantage of
paged or static column DRAMs by indicating whether a requested memory
address is "near" the previously generated address (i.e., within the same
2K-Byte DRAM page). NENE# is valid with CADS# and undefined during
SNPADS#.
NMI I P The Non-Maskable Interrupt request signal indicates that an external
non-maskable interrupt has been generated.
PAllC# 0 CC Potential Allocate indicates to the memory bus controller that the current
write cycle could potentially allocate a cache line. PAllC# is active for
write miss cycles in which lOCK#, PCD and PWT are inactive.
I
1-29