Be#,Be[7:0] - Intel 82496 CACHE CONTROLLER User Manual

HARDWARE INTERFACE
5.2.2.10.
BE#,BE[7:0]#
BE[7:0]# Pentium processor Byte Enables
BE# 82491 Cache SRAM Byte Enable
Controls data for partial writes.
Output from Pentium processor (pins W01, U07, S04, T06, V01, U06, 004, U04),
Input to 82491 Cache SRAM (pin 64)
Synchronous to ClK
Signal Description
Refer to the Pentium™ Processor Data Book for a detailed description of the BE[7:0]# signals.
For a 512K cache configuration (16 82491 Cache SRAM devices), each BE[7:0]# output of the
Pentium processor is connected to the BE# input of two 82491 Cache SRAM devices.
Relation to Other Signals
Pin Symbol
Relation to Other Signals
CDATA[7:4] The Pentium processor byte enable outputs are connected to the 82491 Cache
SRAM CDATA[7:4] pins for 82491 Cache SRAMs configured to be data parity
devices. Refer to section 5.1.6.5.
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