Intel 82496 CACHE CONTROLLER User Manual page 10

CONTENTS
CHAPTERS
HARDWARE INTERFACE Page
5.1. MEMORY BUS CONTROLLER CONSiDERATIONS ................................................... 5-1
5.1 .1. Cycle Control ............................................................................................................ 5-2
5.1.1.1. IDENTIFYING AND EXECUTING CyCLES .......................................................... 5-4
5.1.1.1.1. Read Hit ............................................................................................................ 5-6
5.1.1.1.2. Cacheable Read Miss ....................................................................................... 5-6
5.1.1.1.3. Non-Cacheable Read Miss ............................................................................... 5-7
5.1.1 .1 .4. Write Hit [EJ, [M] ................................................................................................ 5-7
5.1 .1 .1 .5. Write Hit lSI ....................................................................................................... 5-7
5.1.1.1.6. Write Miss: No Allocation, Allocation ................................................................ 5-7
5.1.1.1.7. Replacement. .................................................................................................... 5-8
5.1.1 .1.8. Snoop Write Back ............................................................................................. 5-8
5.1.1.1.9. Locked .............................................................................................................. 5-8
5.1.1.1.10. Cache-To-Cache Transfer ................................................................................ 5-9
5.1.1.1.11. Read For Ownership ......................................................................................... 5-9
5.1 .1 .1.12. 1/0 Cycles ....................................................................................................... 5-10
5.1 .1 .1.13. Special Cycles ................................................................................................ 5-1 0
5.1.1.1.14. FLUSH and SYNC Cycles .............................................................................. 5-10
5.1.2. Snooping ................................................................................................................. 5-11
5.1.2.1. CHOOSING A SNOOPING MODE ..................................................................... 5-11
5.1.2.1.1. Synchronous Snooping Mode ......................................................................... 5-11
5.1.2.1.2. Asynchronous Snooping Mode ....................................................................... 5-12
5.1.2.1.3. Strobed Snooping Mode ................................................................................. 5-13
5.1.2.2. SNOOP OPERATION ......................................................................................... 5-14
5.1.2.3. SNOOP BLOCKING ............................................................................................ 5-17
5.1.2.4. WHEN SNOOPING IS NOT ALLOWED ............................................................. 5-19
5.1.2.5. SNOOPING DURING LOCKED CyCLES ........................................................... 5-20
5.1.2.5.1. Snooping During Split Locked Cycles ............................................................. 5-21
5.1.2.6. SNOOP WRITE BACK CyCLES ......................................................................... 5-21
5.1.3. Address Integrity ..................................................................................................... 5-22
5.1.3.1. CPU BUS ADDRESS PARITY ............................................................................ 5-22
5.1.3.2. MEMORY BUS ADDRESS PARITY ................................................................... 5-22
5.1.4. Data Control ............................................................................................................ 5-23
5.1.4.1. CPU DATA BUS TRANSFER CONTROL ........................................................... 5-24
5.1.5. Memory Bus Mode Selection .................................................................................. 5-24
5.1.6. 82491 Cache SRAM Intelligent Dual-Ported Cache Memory ................................. 5-25
5.1.6.1. 82491 CACHESRAMDATAPATH .................................................................... 5-25
5.1.6.2. . MEMORY CYCLE BUFFERS ............................................................................. 5-26
5.1.6.3. WRITE-BACK AND SNOOP BUFFERS ............................................................. 5-26
5.1.6.4. MEMORY BUS CONTROL SiGNALS ................................................................. 5-27
5.1.6.5. 82491 CACHE SRAM PARITY DEViCES ........................................................... 5-28
5.1.7. Signal Synchronization ........................................................................................... 5-29
5.1.8. Warm Reset ............................................................................................................ 5-30
5.1.9. Handling of Large Caches I Larger Line Sizes ....................................................... 5-30
5.1.10. 82496 Cache Controller Guaranteed Signal Relationships .................................... 5-31
5.1.11. 82496 Cache Controller Cycle Progress Requirements ......................................... 5-32
5.1.12. 82496 Cache Controller Input Signal Recognition Requirements ........................... 5-32
5.1.13. 82496 Cache Controller and 82491 Cache SRAM CRDY# Requirements ............. 5-32
5.1.14. 82496 Cache Controller Cycle Attribute Sampling Requirements .......................... 5-33
5.1.15. Pentium Processor, 82496 Cache Controller, and 82491 Cache
5.1.16.
5.1.17.
5.1.18.
I
SRAM BRDY# Requirements ................................................................................. 5-33
82496 Cache Controller Cycle Progress Signal Sampling Requirements .............. 5-34
82491 Cache SRAM Data Control Signal Requirements ........................................ 5-35
Semaphore (Strong Write Ordering) Consistency .................................................. 5-35
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