Non Cacheable Read Miss Cycles - Intel 82496 CACHE CONTROLLER User Manual

MEMORY BUS FUNCTIONAL DESCRIPTION
6.1.3.
Non Cacheable Read Miss Cycles
10 11 12 13 14 15 16 17 18 19 20 21
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1. In strobed mode, MISTS is used in place of MSRDY to indicate data transfer onto the memory
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Figure 6-4. Non Cacheable Read Miss
Figure 6-4 illustrates a sequence of pipelined read misses that are non-cacheable by the CPU.
The first two cycles (A, B) are also non-cacheable by the 82496 Cache Controller (e.g.
MCACHE# is inactive), while the other two (C, D) are potentially cacheable by the 82496
Cache Controller (active MCACHE#), but not cacheable by the memory bus (inactive MKEN#
during KWEND#). This example assumes that cycles A and B are single transaction read
misses (length::;:1), thus CACHE# is inactive. Cycles C and D are not cacheable due to an
active cache disable bit in the current page table (PCD active).
Note the BLEC# signal. The 82496 Cache Controller deactivates BLEC# immediately upon
detecting the CPU read request (clock 2) in order to keep the byte enable information latched
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6-9