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Intel 87C196CA Supplement To User’s Manual

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8XC196Lx Supplement to
8XC196Kx, 8XC196Jx,
87C196CA User's Manual
August 2004
Order Number: 272973-003

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Summary of Contents for Intel 87C196CA

  • Page 1 8XC196Lx Supplement to 8XC196Kx, 8XC196Jx, 87C196CA User’s Manual August 2004 Order Number: 272973-003...
  • Page 2 Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications.

  • Page 3: Table Of Contents

    CHAPTER 1 GUIDE TO THIS MANUAL MANUAL CONTENTS ... 1-1 RELATED DOCUMENTS ... 1-2 CHAPTER 2 ARCHITECTURAL OVERVIEW MICROCONTROLLER FEATURES ... 2-1 BLOCK DIAGRAM... 2-2 INTERNAL TIMING... 2-2 EXTERNAL TIMING ... 2-5 INTERNAL PERIPHERALS ... 2-6 2.5.1 I/O Ports ...2-7 2.5.2 Synchronous Serial I/O Port ...2-7 2.5.3...
  • Page 4 8XC196L X SUPPLEMENT CHAPTER 6 SYNCHRONOUS SERIAL I/O PORT SSIO 0 CLOCK REGISTER... 6-1 SSIO 1 CLOCK REGISTER... 6-2 CHAPTER 7 EVENT PROCESSOR ARRAY EPA FUNCTIONAL OVERVIEW ... 7-1 7.1.1 EPA Mask Registers ...7-4 7.1.2 EPA Pending Registers ...7-5 7.1.3 EPA Interrupt Priority Vector Register ...7-6 CHAPTER 8 J1850 COMMUNICATIONS CONTROLLER...
  • Page 5 PROGRAMMING THE J1850 CONTROLLER ... 8-16 8.6.1 Programming the J1850 Command (J_CMD) Register ...8-16 8.6.2 Programming the J1850 Configuration (J_CFG) Register ...8-18 8.6.3 Programming the J1850 Delay Compensation (J_DLY) Register ...8-19 8.6.4 Programming the J1850 Status (J_STAT) Register ...8-21 CHAPTER 9 MINIMUM HARDWARE CONSIDERATIONS IDENTIFYING THE RESET SOURCE...
  • Page 6 8XC196L X SUPPLEMENT Figure 8XC196L x Block Diagram ...2-2 Clock Circuitry (87C196LA, LB Only) ...2-3 Internal Clock Phases (Assumes PLL is Bypassed)...2-4 Effect of Clock Mode on Internal CLKOUT Frequency...2-5 Unerasable PROM 1 (USFR1) Register (LA, LB Only) ...2-6 Register File Address Map ...3-3 Interrupt Mask (INT_MASK) Register...4-3 Interrupt Mask 1 (INT_MASK1) Register...4-4 Interrupt Pending (INT_PEND) Register ...4-5...
  • Page 7 Figure 11-1 Slave Programming Circuit...11-3 11-2 Serial Port Programming Circuit ...11-4 87C196LA 52-pin PLCC Package ... A-3 87C196LB 52-pin PLCC Package ... A-5 83C196LD 52-pin PLCC Package... A-7 FIGURES CONTENTS Page...
  • Page 8 8XC196L X SUPPLEMENT Table Related Documents ...1-2 Features of the 8XC196L x and 8XC196K x Product Famiies ...2-1 State Times at Various Frequencies ...2-4 Relationships Between Input Frequency, Clock Multiplier, and State Times ...2-5 UPROM Programming Values and Locations ...2-6 Address Map ...3-1 Register File Memory Addresses ...3-3 8XC196L x Peripheral SFRs ...3-4...

  • Page 9: Guide To This Manual

    Guide to This Manual...

  • Page 11: Manual Contents

    CHAPTER 1 GUIDE TO THIS MANUAL This document is a supplement to the 8XC196Kx, 8XC196Jx, 87C196CA Microcontroller Family User’s Manual. It describes the differences between the 8XC196Lx and the 8XC196Kx family of microcontrollers. For information not found in this supplement, please consult the 8XC196Kx, 8XC196Jx, 87C196CA Microcontroller Family User’s Manual (order number 272258) or the...

  • Page 12: Related Documents

    Table 1-1 lists additional documents that you may find useful in designing systems incorporating the 8XC196Lx microcontrollers. Title and Description 8XC196Kx, 8XC196Jx, 87C196CA Microcontroller Family User’s Manual 87C196LA-20 MHz CHMOS 16-Bit Microcontroller Automotive datasheet 87C196LB-20 MHz CHMOS 16-Bit Microcontroller Automotive datasheet 83C196LD CHMOS 16-Bit Microcontroller Automotive datasheet Table 1-1.

  • Page 13: Architectural Overview

    Architectural Overview...

  • Page 15: Microcontroller Features

    This chapter describes architectural differences between the 8XC196Lx (87C196LA, 87C196LB, and 83C196LD) and the 8XC196Kx (8XC196Kx, 8XC196Jx, and 87C196CA) microcontroller families. Both the 8XC196Lx and the 8XC196Kx are designed for high-speed calculations and fast I/O, and share a common architecture and instruction set with few deviations. This chapter provides a high-level overview of the deviations between the two families.

  • Page 16: Block Diagram

    8XC196L X SUPPLEMENT BLOCK DIAGRAM Figure 2-1 is a simplified block diagram that shows the major blocks within the microcontroller. Observe that the slave port peripheral does not exist on the 8XC196Lx. Core (CPU, Memory Controller) Clock and Power Mgmt. Note: The J1850 peripheral is unique to the 87C196LB device.

  • Page 17: Clock Circuitry (87C196La, Lb Only)

    XTAL1 XTAL1 XTAL2 Disable Oscillator (Powerdown) Figure 2-2. Clock Circuitry (87C196LA, LB Only) The rising edges of PH1 and PH2 generate the internal CLKOUT signal (Figure 2-3). The clock circuitry routes separate internal clock signals to the CPU and the peripherals to provide flexibil- ity in power management.

  • Page 18: Internal Clock Phases (Assumes Pll Is Bypassed)

    8XC196L X SUPPLEMENT XTAL1 CLKOUT Phase 1 Figure 2-3. Internal Clock Phases (Assumes PLL is Bypassed) The combined period of phase 1 and phase 2 of the internal CLKOUT signal defines the basic time unit known as a state time or state. Table 2-2 lists state time durations at various frequencies. Table 2-2.

  • Page 19: External Timing

    XTAL1 (16 MHz) PLLEN = 0 t = 62.5ns Internal CLKOUT PLLEN = 1 t = 31.25ns Internal CLKOUT Figure 2-4. Effect of Clock Mode on Internal CLKOUT Frequency Table 2-3. Relationships Between Input Frequency, Clock Multiplier, and State Times XTAL (Frequency PLLEN...

  • Page 20: Internal Peripherals

    You can verify a UPROM bit to make sure it programmed, but you cannot erase it. For this rea- son, Intel cannot test the bits before shipment. However, Intel does test the features that the UP- ROM bits enable, so the only undetectable defects are (unlikely) defects within the UPROM cells themselves.

  • Page 21: I/O Ports

    2.5.1 I/O Ports The I/O ports of the 8XC196Lx are functionally identical to those of the 8XC196Jx. However, on the 87C196LA and LB the reset state level of all 41 general-purpose I/O pins has changed from a weak logic “1” (wk1) to a weak logic “0” (wk0). 2.5.2 Synchronous Serial I/O Port The synchronous serial I/O (SSIO) port on the 8XC196Lx has been enhanced, implementing two...

  • Page 23: Address Space

    Address Space...

  • Page 25: Address Partitions

    This chapter describes the differences in the address space of the 8XC196Lx from that of the 8XC196Kx. ADDRESS PARTITIONS Table 3-1 is an address map of the 8XC196Lx and 8XC196Kx microcontroller family members. Device and Hex Address Range FFFF FFFF FFFF FFFF A000...

  • Page 26: Register File

    8XC196L X SUPPLEMENT Table 3-1. Address Map (Continued) Device and Hex Address Range 1BFF 1BFF 1BFF — 0500 0500 0600 04FF 04FF — — 0400 0400 03FF 05FF — — 0200 0180 03FF 01FF 017F 02FF 0100 0100 0100 0100 00FF 00FF 00FF...

  • Page 27: Register File Address Map

    Address 03FFH Upper Register File 0100H 00FFH Lower Register File 0000H Figure 3-1. Register File Address Map Table 3-2. Register File Memory Addresses Device and Hex Address Range CA,JT,KT LA, LB JR, KR 1DFF — — — 1C00 03FF 03FF 02FF 01FF 0100...

  • Page 28: Peripheral Special-Function Registers

    8XC196L X SUPPLEMENT PERIPHERAL SPECIAL-FUNCTION REGISTERS Table 3-3 lists the peripheral SFR addresses. Highlighted addresses are unique to the 8XC196Lx. Table 3-3. 8XC196L x Peripheral SFRs Ports 3, 4, 5, and UPROM SFRs Address High (Odd) Byte Low (Even) Byte 1FFEH P4_PIN P3_PIN...
  • Page 29 Table 3-3. 8XC196L x Peripheral SFRs (Continued) SIO and SSIO SFRs Address High (Odd) Byte Low (Even) Byte 1FBEH Reserved Reserved 1FBCH SP_BAUD (H) SP_BAUD (L) 1FBAH SP_CON SBUF_TX 1FB8H SP_STATUS SBUF_RX 1FB6H SSIO1_CLK Reserved 1FB4H SSIO0_CLK SSIO_BAUD 1FB2H SSIO1_CON SSIO1_BUF 1FB0H SSIO0_CON...

  • Page 30: Windowing

    Base for 32-byte Window Address (00E0–00FFH) Peripheral SFRs 1FE0H 7FH (Note) 1FC0H 1FA0H 1F80H 1F60H 1F40H 1F20H 1F00H CAN Peripheral SFRs (87C196CA Only) 1EE0H 1EC0H 1EA0H 1E80H 1E60H 1E40H 1E20H 1E00H Register RAM (87C196JV Only) 1DE0H 1DC0H 1DA0H 1D80H 1D60H...
  • Page 31 Table 3-4. Windows (Continued) WSR Value Base for 32-byte Window Address (00E0–00FFH) Register RAM (87C196JV Only; Continued) 1CE0H 1CC0H 1CA0H 1C80H 1C60H 1C40H 1C20H 1C00H Upper Register File (CA, JT, JV, KT) 03E0H 03C0H 03A0H 0380H 0360H 0340H 0320H 0300H Upper Register File (CA, JT, JV, KT, LA, LB) 02E0H 02C0H...
  • Page 32 8XC196L X SUPPLEMENT Table 3-4. Windows (Continued) WSR Value Base for 32-byte Window Address (00E0–00FFH) Upper Register File (CA, JR, JT, JV, KR, KT, LA, LB, LD) 0160H 0140H 0120H 0100H NOTE: Locations 1FE0–1FFFH contain memory-mapped SFRs that cannot be accessed through a window.

  • Page 33: Standard And Pts Interrupts

    Standard and PTS Interrupts...

  • Page 35: Interrupt Sources, Vectors, And Priorities

    CHAPTER 4 STANDARD AND PTS INTERRUPTS The interrupt structure of the 8XC196Lx is the same as that of the 8XC196Jx. The only difference is that the slave port interrupts (INT08:06) now support the J1850 controller peripheral. INTERRUPT SOURCES, VECTORS, AND PRIORITIES Table 4-1 lists the 8XC196Lx’s interrupts sources, default priorities (30 is highest and 0 is low- est), and vector addresses.

  • Page 36: Interrupt Registers

    8XC196L X SUPPLEMENT Table 4-1. Interrupt Sources, Vectors, and Priorities Interrupt Source Mnemonic Nonmaskable Interrupt EXTINT Pin EXTINT Reserved — SIO Receive SIO Transmit SSIO Channel 1 Transfer SSIO1 SSIO Channel 0 Transfer SSIO0 J1850 Status (LB only) J1850ST Reserved (LA, LD) —...

  • Page 37: Interrupt Mask Registers

    4.2.1 Interrupt Mask Registers Figures 4-1 and 4-2 illustrate the interrupt mask registers for the 8XC196Lx microcontrollers. INT_MASK The interrupt mask (INT_MASK) register enables or disables (masks) individual interrupt requests. (The EI and DI instructions enable and disable servicing of all maskable interrupts.) INT_MASK is the low byte of the processor status word (PSW).

  • Page 38: Interrupt Pending Registers

    8XC196L X SUPPLEMENT INT_MASK1 The interrupt mask 1 (INT_MASK1) register enables or disables (masks) individual interrupt requests. (The EI and DI instructions enable and disable servicing of all maskable interrupts.) INT_MASK1 can be read from or written to as a byte register. PUSHA saves this register on the stack and POPA restores it.

  • Page 39: Interrupt Pending (Int_Pend) Register

    INT_PEND When hardware detects an interrupt request, it sets the corresponding bit in the interrupt pending (INT_PEND or INT_PEND1) registers. When the vector is taken, the hardware clears the pending bit. Software can generate an interrupt by setting the corresponding interrupt pending bit. —...

  • Page 40: Peripheral Transaction Server Registers

    8XC196L X SUPPLEMENT INT_PEND1 When hardware detects an interrupt request, it sets the corresponding bit in the interrupt pending (INT_PEND or INT_PEND1) registers. When the vector is taken, the hardware clears the pending bit. Software can generate an interrupt by setting the corresponding interrupt pending bit. EXTINT LA, LD EXTINT...

  • Page 41: Pts Select (Ptssel) Register

    PTSSEL The PTS select (PTSSEL) register selects either a PTS microcode routine or a standard interrupt service routine for each interrupt request. Setting a bit selects a PTS microcode routine; clearing a bit selects a standard interrupt service routine. In PTS modes that use the PTSCOUNT register, hardware clears the corresponding PTSSEL bit when PTSCOUNT reaches zero.

  • Page 42: Pts Service (Ptssrv) Register

    8XC196L X SUPPLEMENT PTSSRV The PTS service (PTSSRV) register is used by the hardware to indicate that the final PTS interrupt has been serviced by the PTS routine. When PTSCOUNT reaches zero, hardware clears the corresponding PTSSEL bit and sets the PTSSRV bit, which requests the end-of-PTS interrupt. When the end-of-PTS interrupt is called, hardware clears the PTSSRV bit.

  • Page 43: I/O Ports

    I/O Ports...

  • Page 45: I/O Ports Overview

    The I/O ports of the 8XC196Lx are functionally identical to those of the 8XC196Jx. However, on the 87C196LA and LB, the reset state level of all 41 general-purpose I/O pins has changed from a weak logic “1” (wk1) to a weak logic “0” (wk0). This chapter outlines the differences between the 87C196LA, LB and the 8XC196Kx controllers.
  • Page 46 8XC196L X SUPPLEMENT input signals set SFDIR. Even if a pin is to be used in special-function mode, you must still ini- tialize the pin as an input or output by writing to the port direction register. Resistor R1 provides ESD protection for the pin. Input signals are buffered. The standard ports use Schmitt-triggered buffers for improved noise immunity.

  • Page 47: Configuring Ports 1, 2, 5, And 6 (Bidirectional Ports)

    Internal Bus P x _REG SFDATA P x _DRV SFDIR P x _MODE Read Port RESET# Any Write to P x _MODE Figure 5-1. Ports 1, 2, 5, and 6 Internal Structure (87C196LA, LB Only) 5.2.1 Configuring Ports 1, 2, 5, and 6 (Bidirectional Ports) Using the port mode register, you can individually configure each pin for port 1, 2, 5, and 6 to operate either as a general-purpose I/O signal (I/O mode) or as a special-function signal (special- function mode).

  • Page 48: Special Bidirectional Port Considerations

    8XC196L X SUPPLEMENT impedance input, or open-drain output. The port direction and data output registers select the con- figuration for each pin. Complementary output means that the microcontroller drives the signal high or low. High-impedance input means that the microcontroller floats the signal. Open-drain output means that the microcontroller drives the signal low or floats it.

  • Page 49: Internal Structure For Ports 3 And 4 (Address/Data Bus)

    in using this pin. Be certain that your system meets the V prevent inadvertent entry into ONCE mode or a test mode. Following reset, P2.7/CLKOUT carries the strongly driven CLKOUT signal. It is not held low. When P2.7/CLKOUT is configured as CLKOUT, it is always a complementary output.

  • Page 50: Ports 3 And 4 Internal Structure (87C196La, Lb Only)

    8XC196L X SUPPLEMENT Internal Bus P x _REG Address/Data Bus Control Select 0 = Address/Data 1 = I/O P34_DRV Read Port RESET# Figure 5-2. Ports 3 and 4 Internal Structure (87C196LA, LB Only) RESET# Sample Latch P x _PIN Buffer PH1 Clock 300ns Delay I/O Pin...

  • Page 51: Synchronous Serial I/O Port

    Synchronous Serial I/O Port...

  • Page 53: Ssio 0 Clock Register

    SYNCHRONOUS SERIAL I/O PORT The synchronous serial I/O (SSIO) port on the 8XC196Lx has been enhanced, implementing two new special function registers (SSIO0_CLK and SSIO1_CLK) that allow you to select the oper- ating mode and configure the phase and polarity of the serial clock signals. SSIO 0 CLOCK REGISTER The SSIO 0 clock (SSIO_CLK) register selects the phase and polarity for the SC0 clock signal.

  • Page 54: Ssio 1 Clock Register

    8XC196L X SUPPLEMENT For transmissions, SSIO0_CLK determines whether the SSIO shifts out data bits on rising or fall- ing clock edges. For receptions, SSIO0_CLK determines whether the SSIO samples data bits on rising or falling clock edges. SSIO 1 CLOCK REGISTER SSIO1_CLK selects the SSIO mode of operation (standard, duplex, or channel-select), enables the channel-select master contention interrupt request, and selects the phase and polarity for the serial clock (SC1) for channels.
  • Page 55 SSIO1_CLK (Continued) The SSIO 1 clock (SSIO1_CLK) register selects the SSIO mode of operation (standard, duplex, or channel-select), enables the channel-select master contention interrupt request, and selects the phase and polarity for the serial clock (SC1) for channel 1. — —...

  • Page 57: Event Processor Array

    Event Processor Array...

  • Page 59: Epa Functional Overview

    8XC196LA, LB EPA3:0 and EPA9:8 8XC196LD EPA3:0 and EPA9:8 87C196CA, 8XC196J x EPA3:0 and EPA9:8 8XC196K x The 8XC196Lx’s EPA performs input and output functions associated with two timer/counters, timer 1 and timer 2, as depicted in Figures 7-1 and 7-2.

  • Page 60: Epa Block Diagram (87C196La, Lb Only)

    8XC196L X SUPPLEMENT Timer-Counter Unit TIMER1 TIMER2 EPA 3:0 EPA8 / COMP0 EPA9 / COMP1 Figure 7-1. EPA Block Diagram (87C196LA, LB Only) Capture/Compare EPA 3:0 Interrupts Channel 0–3 Capture/Compare Channel 6–7 Capture/Compare Channel 8 Indirect Compare-only Interrupt Channel 0 Processor Logic Capture/Compare...

  • Page 61: Epa Block Diagram (83C196Ld Only)

    Timer-Counter Unit TIMER1 TIMER2 Capture/Compare Channel 0–3 EPA 3:0 Capture/Compare Channel 6–7 Capture/Compare EPA8 Channel 8 Capture/Compare Channel 9 EPA9 Figure 7-2. EPA Block Diagram (83C196LD Only) EVENT PROCESSOR ARRAY EPA 3:0 Interrupts EPA x Interrupt Indirect Interrupt Processor Logic A5281-01...

  • Page 62: Epa Mask Registers

    8XC196L X SUPPLEMENT 7.1.1 EPA Mask Registers Figures 7-3 and 7-4 illustrate the EPA mask registers, EPA_MASK and EPA_MASK1, for the 8XC196Lx microcontroller family. EPA_MASK The EPA interrupt mask (EPA_MASK) register enables or disables (masks) interrupts associated with the shared EPA x interrupt. —...

  • Page 63: Epa Pending Registers

    7.1.2 EPA Pending Registers Figures 7-5 and 7-6 illustrate the EPA pending registers, EPA_PEND and EPA_PEND1, for the 8XC196Lx microcontroller family. EPA_PEND When hardware detects a pending EPA6–9 or OVR0–3, 8–9 interrupt request, it sets the corresponding bit in the EPA interrupt pending register (EPA_PEND or EPA_PEND1). The EPAIPV register contains a number that identifies the highest priority, active, shared interrupt source.

  • Page 64: Epa Interrupt Priority Vector Register

    8XC196L X SUPPLEMENT 7.1.3 EPA Interrupt Priority Vector Register Figure 7-7 illustrates the EPA interrupt priority vector (EPAIPV) register for the 8XC196Lx mi- crocontroller family. EPAIPV When an EPA x interrupt occurs, the EPA interrupt priority vector (EPAIPV) register contains a number that identifies the highest priority, active, multiplexed interrupt source (see Table 7-2).

  • Page 65: J1850 Communications Controller

    J1850 Communications Controller...

  • Page 67: J1850 Functional Overview

    J1850 COMMUNICATIONS CONTROLLER The J1850 communications controller manages communications between multiple network nodes. This integrated peripheral supports the 10.4 Kb/s VPW (variable pulse width) medium- speed class B in-vehicle network protocol. It also supports both the standard and in-frame re- sponse (IFR) message framing as specified by the Society of Automotive Engineering (SAE) J1850 (revised May 1994) technical standards.

  • Page 68: J1850 Communications Controller Block Diagram

    8XC196L X SUPPLEMENT The J1850 controller can handle network protocol functions including message frame sequenc- ing, bit arbitration, in-frame response (IFR) messaging, error detection, and delay compensation. The J1850 communications controller (Figure 8-2) consists of a control state machine (CSM), symbol synchronization and timing (SST) circuitry, six control and status registers, transmit and receive buffers, and an interrupt handler.

  • Page 69: J1850 Controller Signals And Registers

    J1850 CONTROLLER SIGNALS AND REGISTERS Table 8-1 describes the J1850 controller’s pins, and Table 8-2 describes the control and status registers. Table 8-1. J1850 Controller Signals Signal Type RXJ1850 Receive Carries digital symbols from a remote transceiver to the J1850 controller. TXJ1850 Transmit Carries digital symbols from the J1850 controller to a remote transceiver.

  • Page 70: J1850 Controller Operation

    8XC196L X SUPPLEMENT Table 8-2. Control and Status Registers (Continued) Mnemonic Address INT_MASK 0008H Interrupt Mask INT_MASK1 0013H Interrupt Mask 1 INT_PEND 0009H Interrupt Pending INT_PEND1 0012H Interrupt Pending 1 PTSSEL 0004H PTS Select PTSSRV 0006H PTS Service J1850 CONTROLLER OPERATION This section describes the control state machine (which contains the cyclic redundancy check generator) and the symbol synchronization and timing circuitry for J1850 transmissions and re- ceptions.

  • Page 71: Bus Contention

    8.3.1.2 Bus Contention Bus contention arises when multiple nodes attempt to access and transmit message frames across the J1850 bus simultaneously. This creates a conflict on the bus. The recognition of conflicting symbols or bits on the bus is referred to as contention detection. For example, if a node observes a difference between a symbol it transmits to the J1850 bus and the symbol that it detects on the bus, that node has detected contention to the transmission of its message frame.

  • Page 72: Clock Prescaler

    8XC196L X SUPPLEMENT 8.3.2.1 Clock Prescaler Because the 87C196LB microcontroller can operate at a variety of input frequencies (F clock prescaler circuitry is used to provide a single, internal clock frequency (f/2) to ensure that the J1850 peripheral is clocked at the proper operating frequency. This is accomplished through the programmable clock prescaler bits, PRE1:0 in the J_CFG register (Figure 8-17 on page 8-18).

  • Page 73: Bit Arbitration Example

    "passive 1" "passive 0" Figure 8-3. Huntzicker Symbol Definition for J1850 A symbol is defined as a timing-level formatted bit. The VPW symbol timing requirements stip- ulate that there is one symbol per transition and one transition per symbol. This ensures that a message frame will always result in a uniform square waveform of varying level durations.

  • Page 74: Message Frames

    8XC196L X SUPPLEMENT of arbitration, nodes A, C, and D are all transmitting an “active 0” symbol, thus the idle state of the “passive 1” symbol is overruled in favor of the driven state of the “active 0” symbol. Node C is the next node to discontinue transmitting when it attempts to take control of the bus by transmitting an “active 1”...

  • Page 75: Standard Messaging

    Standard Frame 1-3 Bytes 1-11 Bytes Header Data In-frame Response (IFR) Frame 1-3 Bytes 1-11 Bytes Header Data † The number of data bytes to be transferred is unspecified if 0EH is written to J_CMD3:0. Figure 8-6. J1850 Message Frames A standard message frame is initiated by the responder and contains no more than 11 data bytes to be transmitted.

  • Page 76: Start And End Message Frame Symbols

    8XC196L X SUPPLEMENT (J_CFG.7) and considers whether the IFR message response has a CRC byte appended. Figure 8-7 depicts the SAE preferred, active-level state bit format timing for the NB. 64µS NB for IFR without CRC Figure 8-7. Huntzicker Symbol Definition for the Normalization Bit 8.4.1.4 Start and End Message Frame Symbols Five symbols are used to mark the start and end of a message frame and to allow the J1850 bus...

  • Page 77: Definition For Start And End Of Frame Symbols

    Figure 8-8. Definition for Start and End of Frame Symbols Table 8-4 details the symbol timing characteristics supported by the 87C196LB. Table 8-4. Huntzicker Symbol Timing Characteristics Name Symbol Passive Logic Level 0 Active Passive Logic Level 1 Active Start of Frame Active End of Data Passive...

  • Page 78: In-Frame Response Messaging

    8XC196L X SUPPLEMENT 8.4.2 In-frame Response Messaging There are three types of in-frame response (IFR) message framings: type 1 (a single byte from a single responder), type 2 (a single byte from multiple responders), and type 3 (multiple bytes from a single responder).

  • Page 79: Ifr Messaging Type 3: Multiple Bytes, Single Responder

    In-frame Response (IFR) Frame 1-3 Bytes 1-11 Bytes Header Data † The number of data bytes to be transferred is unspecified if 0EH is written to J_CMD3:0. †† Each D block in the IFR data field represents a byte of data from a different remote node. Figure 8-10.

  • Page 80: J1850 Transmit Message Structure

    8XC196L X SUPPLEMENT J_TX The J1850 transmitter (J_TX) register transfers data in byte increments to the J1850 bus from the microcontroller CPU. This register is buffered to allow for transmission of a second data byte while the first data byte is being shifted out. This byte register can be read or written, and is addressable through windowing .

  • Page 81: Receiving Messages

    An overrun condition can occur on transmission if the transmit buffer, JTX_BUF, is overwritten. 8.5.2 Receiving Messages For a message reception, after a SOF is detected on the bus, the controller starts to shift data sym- bols into the J1850 receive buffer (JRX_BUF) until an entire data byte has been received. This byte is automatically transferred into the J1850 receive (J_RX) register (Figure 8-14) and the sub- sequent byte is written into the empty JRX_BUF.

  • Page 82: Ifr Messages

    8XC196L X SUPPLEMENT If a third byte is received before J_RX is read, a J1850ST core interrupt is generated and the OVR_UNDR (J_STAT.3) bit records a receiver overrun error in the J_STAT register. 8.5.3 IFR Messages In-frame response (IFR) messaging is identical in setup to standard messaging for both transmis- sion and reception.

  • Page 83: J1850 Command (J_Cmd) Register

    J_CMD The J1850 command (J_CMD) register determines the messaging type, specifies the number of bytes to be transmitted in the next message frame, and updates the status of the message transmission in progress. This byte register can be directly addressed through windowing . You must write to this register prior to transmitting every message.

  • Page 84: Programming The J1850 Configuration (J_Cfg) Register

    8XC196L X SUPPLEMENT 8.6.2 Programming the J1850 Configuration (J_CFG) Register The J1850 configuration register (Figure 8-17) selects the proper oscillator prescaler, initiates a transmission break for debugging, invokes clock quadrupling operation, and selects the normal- ization bit format. J_CFG The J1850 configuration (J_CFG) register selects the proper oscilator prescaler, initiates transmission break for debug, invokes clock quadrupling operation, and selects the normalizartion bit format.

  • Page 85: Programming The J1850 Delay Compensation (J_Dly) Register

    J_CFG The J1850 configuration (J_CFG) register selects the proper oscilator prescaler, initiates transmission break for debug, invokes clock quadrupling operation, and selects the normalizartion bit format. This byte register can be directly addressed through windowing . All J1850 bus activity is ignored until you first write to this register.

  • Page 86: J1850 Delay (J_Dly) Register

    8XC196L X SUPPLEMENT J_DLY The J1850 delay (J_DLY) register allows you compensate for the inherent propagation delays and to accurately resolve bus contention during arbitration. This byte register can be directly addressed through windowing . — — — Number Mnemonic —...

  • Page 87: Programming The J1850 Status (J_Stat) Register

    8.6.4 Programming the J1850 Status (J_STAT) Register The J1850 status register (Figure 8-19) provides the current status of the message and the four interrupt sources associated with the J1850 protocol. J_STAT The J1850 status (J_STAT) register provides the current status of the message transfer, the receive and transmit buffers, and the four interrupt sources associated with the J1850 protocol.
  • Page 88 8XC196L X SUPPLEMENT J_STAT The J1850 status (J_STAT) register provides the current status of the message transfer, the receive and transmit buffers, and the four interrupt sources associated with the J1850 protocol. This byte register can be directly addressed through windowing . You must write to this register before transmitting each message.

  • Page 89: Minimum Hardware Considerations

    Minimum Hardware Considerations...

  • Page 91: Identifying The Reset Source

    MINIMUM HARDWARE CONSIDERATIONS This chapter discusses the major hardware consideration differences between the 8XC196Lx and the 8XC196Kx. The 8XC196Lx has implemented a reset source SFR that reveals the source of the most recent reset request. IDENTIFYING THE RESET SOURCE The reset source (RSTSRC) register indicates the source of the last reset that the microcontroller encountered (Figure 9-1).

  • Page 92: Design Considerations For 8Xc196La, Lb, And Ld

    8XC196L X SUPPLEMENT DESIGN CONSIDERATIONS FOR 8XC196LA, LB, AND LD With the exception of a few new multiplexed functions, the 8XC196Lx microcontrollers are pin compatible with the 8XC196Jx microcontrollers. The 8XC196Jx microcontrollers are 52-lead versions of 8XC196Kx microcontrollers. Follow these recommendations to help maintain hardware and software compatibility between the 8XC196Lx, 8XC196Kx, and future microcontrollers.

  • Page 93: Special Operating Modes

    Special Operating Modes...

  • Page 95: 10.1 Internal Timing

    CHAPTER 10 SPECIAL OPERATING MODES The 8XC196Lx’s idle and powerdown modes are the same as those of the 8XC196Kx. However, the clock circuitry has changed, and the on-circuit emulation (ONCE) special-purpose mode op- eration has changed slightly because of the new reset state pin levels that have been implemented. 10.1 INTERNAL TIMING The 87C196LA and LB clock circuitry (Figure 10-1) implements a phase-locked loop and clock multiplier circuitry, which can substantially increase the CPU clock rate while using a lower-fre-...

  • Page 96: 10.2 Entering And Exiting Once Mode

    8XC196L X SUPPLEMENT XTAL1 XTAL1 XTAL2 Disable Oscillator (Powerdown) Figure 10-1. Clock Circuitry (87C196LA, LB Only) 10.2 ENTERING AND EXITING ONCE MODE ONCE mode isolates the device from other components in the system to allow printed-circuit- board testing or debugging with a clip-on emulator. During ONCE mode, all pins except XTAL1, XTAL2, V , and V are weakly pulled either high or low.
  • Page 97 SPECIAL OPERATING MODES an output. If you choose to configure this pin as an input, always hold it low during reset and en- sure that your system meets the V specification to prevent inadvertent entry into ONCE mode. 10-3...

  • Page 99: Programming The Nonvolatile Memory

    Programming the Nonvolatile Memory...

  • Page 101: 11.1 Signature Word And Programming Voltage Values

    PROGRAMMING THE NONVOLATILE MEMORY The 87C196LA and LB microcontrollers contain 24 Kbytes (2000–7FFFH) of one-time-pro- grammable read-only memory (OTPROM). OTPROM is similar to EPROM, but it comes in a windowless package and cannot be erased. You have the option of programming the OTPROM yourself or having the factory program it as a quick-turn ROM product (the latter option may not be available for all devices).

  • Page 102: 11.3 Slave Programming Circuit And Address Map

    Lower interrupt vectors 2000 † Intel manufacturing uses this location to determine whether to program the OFD bit. Customers with quick-ROM (QROM) or masked-ROM (MROM) codes who desire oscillator failure detection should equate this location to the value 0CDEH. 11.3 SLAVE PROGRAMMING CIRCUIT AND ADDRESS MAP Figure 11-1 shows the circuit diagram and Table 11-3 details the address map for slave program- ming of the 87C196LA and LB devices.

  • Page 103: Slave Programming Circuit

    0.1 µF P0.7/PMODE.3 P0.6/PMODE.2 P0.5/PMODE.1 P0.4/PMODE.0 ANGND Figure 11-1. Slave Programming Circuit Table 11-3. Slave Programming Mode Address Map Description OTPROM † † PCCB Programming V Programming V Signature word † These bits program the UPROM cells. Once these bits are programmed, they cannot be erased, and dynamic failure analysis of the device is impossible.

  • Page 104: 11.4 Serial Port Programming Circuit And Address Map

    8XC196L X SUPPLEMENT 11.4 SERIAL PORT PROGRAMMING CIRCUIT AND ADDRESS MAP Figure 11-2 shows the circuit and Table 11-4 details the address map for serial port programming. 0.01 µF 1.8k 1.8k 2N2907 1.8k 1.8k Figure 11-2. Serial Port Programming Circuit 11-4 30 pF XTAL1...

  • Page 105: Serial Port Programming Mode Address Map

    Table 11-4. Serial Port Programming Mode Address Map Description Internal OTPROM External memory Do not address Test ROM and RISM PROGRAMMING THE NONVOLATILE MEMORY Address Range Normal Operation Serial Port Programming Mode 2000–7FFFH — — — A000–FFFFH 4000–9FFFH 2400–3FFFH 2000–23FFH 11-5...

  • Page 107: Signal Descriptions

    Signal Descriptions...

  • Page 109: Functional Groupings Of Signals

    APPENDIX A SIGNAL DESCRIPTIONS This appendix provides reference information for the pin functions of the 8XC196Lx microcon- trollers. FUNCTIONAL GROUPINGS OF SIGNALS Tables A-1, A-2, and A-3 list the signal assignments for the 8XC196Lx microcontrollers, grouped by function. A diagram of each microcontroller shows the pin location of each signal.

  • Page 110: A-1 87C196La Signals Arranged By Functional Categories

    8XC196L X SUPPLEMENT Table A-1. 87C196LA Signals Arranged by Functional Categories Addr & Data Input/Output (Cont’d) Name P2.1 / RXD P2.2 P2.4 P2.6 P2.7 P3.0 P3.1 P3.2 P3.3 P3.4 AD10 P3.5 AD11 P3.6 AD12 P3.7 AD13 P4.0 AD14 P4.1 AD15 P4.2 P4.3 Input/Output...

  • Page 111: A-1 87C196La 52-Pin Plcc Package

    AD14 / P4.6 / PBUS.14 AD13 / P4.5 / PBUS.13 AD12 / P4.4 / PBUS.12 AD11 / P4.3 / PBUS.11 xx87C196LA20 AD10 / P4.2 / PBUS.10 AD9 / P4.1 / PBUS.9 AD8 / P4.0 / PBUS.8 View of component as AD7 / P3.7 / PBUS.7 AD6 / P3.6 / PBUS.6 mounted on PC board...

  • Page 112: A-2 87C196Lb Signals Arranged By Functional Categories

    8XC196L X SUPPLEMENT Table A-2. 87C196LB Signals Arranged by Functional Categories Addr & Data Input/Output (Cont’d) Name P2.1 / RXD P2.2 P2.4 / RXJ1850 P2.6 / TXJ1850 P2.7 P3.0 P3.1 P3.2 P3.3 P3.4 AD10 P3.5 AD11 P3.6 AD12 P3.7 AD13 P4.0 AD14 P4.1...

  • Page 113: A-2 87C196Lb 52-Pin Plcc Package

    AD14 / P4.6 / PBUS.14 AD13 / P4.5 / PBUS.13 AD12 / P4.4 / PBUS.12 AD11 / P4.3 / PBUS.11 xx87C196LB20 AD10 / P4.2 / PBUS.10 AD9 / P4.1 / PBUS.9 AD8 / P4.0 / PBUS.8 View of component as AD7 / P3.7 / PBUS.7 AD6 / P3.6 / PBUS.6 mounted on PC board...

  • Page 114: A-3 83C196Ld Signals Arranged By Functional Categories

    8XC196L X SUPPLEMENT Table A-3. 83C196LD Signals Arranged by Functional Categories Addr & Data Input/Output Name Name P1.0/EPA0/T2CLK P1.1/EPA1 P1.2/EPA2/T2DIR P1.3/EPA3 P2.0/TXD P2.1/RXD P2.2 P2.4 P2.6 P2.7 AD10 P3.0 AD11 P3.1 AD12 P3.2 AD13 P3.3 AD14 P3.4 AD15 P3.5 P3.6 Input P3.7 Name...

  • Page 115: A.2 Default Conditions

    AD14 / P4.6 AD13 / P4.5 AD12 / P4.4 AD11 / P4.3 AD10 / P4.2 AD9 / P4.1 AD8 / P4.0 AD7 / P3.7 AD6 / P3.6 AD5 / P3.5 AD4 / P3.4 AD3 / P3.3 AD2 / P3.2 Figure A-3. 83C196LD 52-pin PLCC Package DEFAULT CONDITIONS Table A-5 lists the values of the signals for the 87C196LA and 87C196LB during various oper- ating conditions.

  • Page 116: A-5 87C196La, Lb Default Signal Conditions

    8XC196L X SUPPLEMENT Table A-5. 87C196LA, LB Default Signal Conditions Port Alternate Signals Functions P0.7:2 ACH7:2 P1.0 EPA0/T2CLK P1.1 EPA1 P1.2 EPA2/T2DIR P1.3 EPA3 P2.0 P2.1 P2.2 EXTINT P2.4 RXJ1850 (LB only) P2.6 ONCE/TXJ1850 (LB only) P2.7 CLKOUT P3.7:0 AD7:0 P4.7:0 AD15:8 P5.0...

  • Page 117: A-6 83C196Ld Default Signal Conditions

    Table A-6. 83C196LD Default Signal Conditions Port Alternate Signals Functions P0.7:2 — P1.0 EPA0/T2CLK P1.1 EPA1 P1.2 EPA2/T2DIR P1.3 EPA3 P2.0 P2.1 P2.2 EXTINT P2.4 — P2.6 ONCE P2.7 CLKOUT P3.7:0 AD7:0 P4.7:0 AD15:8 P5.0 ALE/ADV# P5.2 WR#/WRL# P5.3 P6.0 EPA8 P6.1 EPA9...
  • Page 119 Glossary...
  • Page 121 This glossary defines acronyms, abbreviations, and terms that have special meaning in this man- ual. (Chapter 1 discusses notational conventions and general terminology.) absolute error accumulator actual characteristic A/D converter assert attenuation bit arbitration break-before-make The maximum difference between corresponding actual and ideal code transitions.
  • Page 122 8XC196L X SUPPLEMENT byte BYTE CCBs CCRs channel-to-channel matching error characteristic chip-select unit clear code code center code transition code width Glossary-2 Any 8-bit unit of data. An unsigned, 8-bit variable with values from 0 through 2 –1. Chip configuration bytes. The chip configuration registers (CCRs) are loaded with the contents of the CCBs after a reset.
  • Page 123 contention crosstalk DC input leakage deassert demultiplexed bus differential nonlinearity doping double-word DOUBLE-WORD The detection of conflicting symbols or bits on the bus. See off-isolation. Leakage current from an analog input pin to ground or to the reference voltage (V The act of making a signal inactive (disabled).
  • Page 124 8XC196L X SUPPLEMENT external address far constants far data feedthrough full-scale error hold latency ideal characteristic input leakage input series resistance integer INTEGER Glossary-4 A 21-bit address is presented on the microcontroller’s pins. The address decoded by an external device depends on how many of these address pins the external system uses.
  • Page 125 internal address interrupt controller interrupt latency interrupt service routine interrupt vector J1850 linearity errors LONG-INTEGER The 24-bit address that the microcontroller generates. See also external address. The module responsible for handling interrupts that are to be serviced by interrupt service routines that you provide.
  • Page 126 8XC196L X SUPPLEMENT maskable interrupts monotonic multiplexed bus n-channel FET n-type material near constants near data no missing codes Glossary-6 All interrupts except stack overflow, unimplemented opcode, and software trap. Maskable interrupts can be disabled (masked) by the individual mask bits in the interrupt mask registers, and their servicing can be disabled by the DI (disable interrupt service) instruction.
  • Page 127 nonlinearity nonmaskable interrupts npn transistor off-isolation p-channel FET p-type material phase-locked loop The maximum deviation of code transitions of the terminal-based characteristic from the corre- sponding code transitions of the ideal characteristic. Interrupts that cannot be masked (disabled) and cannot be assigned to the PTS for processing. The nonmaskable interrupts are stack overflow, unimple- mented opcode, software trap, and NMI.
  • Page 128 8XC196L X SUPPLEMENT prioritized interrupt program memory protected instruction PTSCB PTS control block PTS cycle PTS interrupt PTS mode PTS routine PTS transfer Glossary-8 NMI, stack overflow, or any maskable interrupt. Two of the nonmaskable interrupts (unimplemented opcode and software trap) are not prioritized; they vector directly to the interrupt service routine when executed.
  • Page 129 PTS vector QUAD-WORD quantizing error RALU repeatability error reserved memory resolution sample capacitor sample delay sample delay uncertainty sample time A location in special-purpose memory that holds the starting address of a PTS control block. An unsigned, 64-bit variable with values from 0 through 2 –1.
  • Page 130 8XC196L X SUPPLEMENT sample time uncertainty sample window sampled inputs SHORT-INTEGER sign extension sink current source current special interrupt Glossary-10 The variation in the sample time. The period of time that begins when the sample capacitor is attached to a selected channel of an A/D converter and ends when the sample capacitor is disconnected from the selected channel.
  • Page 131 special-purpose memory standard interrupt state time (or state) successive approximation temperature coefficient temperature drift terminal-based characteristic transfer function transfer function errors UART A partition of memory used for storing the interrupt vectors, PTS vectors, chip configuration bytes, and several reserved locations. Any maskable interrupt that is assigned to the interrupt controller for processing by an interrupt service routine.
  • Page 132 8XC196L X SUPPLEMENT rejection wait state watchdog timer word WORD zero extension zero-offset error Glossary-12 The property of an A/D converter that causes it to ignore (reject) changes in V so that the actual characteristic is unaffected by those changes. The effectiveness of V rejection is measured by the ratio of the change in V...
  • Page 133 Index...
  • Page 135 Address map, 3-1 Address partitions map, 3-1 OTPROM, 11-1 program memory, 11-1 special-purpose memory, 11-1 ALE, idle, powerdown, reset status, A-8, A-9 Block diagram 8XC196Lx, 2-2 CLKOUT and internal timing, 2-2–2-4 idle, powerdown, reset status, A-8, A-9 output frequency, 2-5 reset status, 5-2 Clock circuitry, 2-3, 10-2 delay register, 8-20...
  • Page 136 Period (t), 2-4 Port 0 idle, powerdown, reset status, A-8, A-9 overview, 5-1 Port 1 configuring, 5-3 idle, powerdown, reset status, A-8, A-9 overview, 5-1 Port 2 configuring, 5-3 idle, powerdown, reset status, A-8, A-9 overview, 5-1 P2.7 reset status, 5-2 Port 3 idle, powerdown, reset status, A-8, A-9 internal structure, 5-5...

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