Data Control - Intel 82496 CACHE CONTROLLER User Manual

HARDWARE INTERFACE
bit (MAp) valid for each cycle it initiates on the memory bus. The MBC can ignore this signal
if address parity is not supported.
During 82496 Cache Controller/82491 Cache SRAM snoop cycles, MAP may be driven by the
MBC to indicate the line address parity for the snooped address (the specific 82496 Cache
Controller address pins are configuration dependent - refer to Table 4-3). If the 82496 Cache
Controller detects a memory address parity error (based on the memory bus line address and
the MAP bit driven by the MBC), it drives the MAPERR# signal low (refer to the MAPERR#
detailed pin description for details) to flag the error to the memory bus controller. Again, the
MBC can ignore this error indication if memory bus address parity is not supported.
MAPERR# for any particular snoop operation is valid either from two CLKs after SNPSTB#
(synchronous snoop mode) or one CLK after SNPCYC# (clocked and strobed snoop modes)
until that same time during the subsequent snoop operation. MAPERR# is driven with the
timings shown in Figure 5-17 for synchronous snooping mode and Figure 5-18 for the
asynchronous snooping modes (clocked and strobed).
ClK
SNPSTB#
MAPERR#
~ __ ~ __ ~~X~~~~IV~Al=ID~A~I ____ ~~xwl~~=ll~D~B~I __ ~_
CDB45
Figure 5-17. MAPERR# Timing for Synchronous Snoop Mode
ClK
SNPCYC#
MAPERR#
~ __ ~ ____ ~~X~~-«~IV~A=lID~A~I __ ~X~I ____ ~lv~A=L1D~B~1~ __ ~
I
CDB44
Figure 5-18. MAPERR# Timing for Asynchronous Snoop Modes
5.1.4. Data Control
All data control is handled by the MBC, including handshaking data into and out of the 82496
Cache Controller/82491 Cache SRAM and CPU, freezing data for allocations, pipelining data
on the memory bus and retrying data as necessary.
The 82491 Cache SRAM data path is separate from the address path. These paths do not have
to operate at the same clock frequency, and it is possible, for example, for the 82491 Cache
I
5-23