Wba - Intel 82496 CACHE CONTROLLER User Manual

HARDWARE INTERFACE
5.2.2.144. WBA
WBA Write Back Buffer Address
Indicates which line is loaded into replacement write back buffer.
Output from 82496 Cache Controller (pin N15), Input to 82491 Cache SRAM (pin
38)
Synchronous to ClK
Signal Description
WBA is driven to the 82491 Cache SRAM to indicate which line will be written back during
the replacement write back. If the 82496 Cache Controller uses 2 lines per sector, WBA
distinguishes to the 82491 Cache SRAM which line is to be written back. WBA low selects
line 1 and WBA high selects line 2.
In
configurations with 1 line per sector (1,2,4,5), WBA is driven low to the 82491 Cache
SRAM during write back cycles. In configurations with 2 lines per sector (3), WBA indicates
which line in the sector is being accessed. If WBA is low, the first line in the sector is being
accessed. If WBA is high, the second line in the sector is being accessed.
WBA is driven high to the 82491 Cache SRAM for snoop cycles which hit the replacement
write back buffer and low for cycles which miss the replacement write back buffer.
Relation to Other Signals
Pin Symbol Relation to Other Signals
SEC2#
WBA shares a pin with the configuration signal SEC2#.
WBWE# WBA and WBTYP are sampled by the 82491 Cache SRAM with WBWE#.
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