Intel 82496 CACHE CONTROLLER User Manual page 35

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MEMORY BUS CONTROLLER/MEMORY BUS
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Figure 1-7_ Brief Pin Description Table Cross Reference
In the following tables, a signal name in brackets "[ ]" represents a configuration input signal
sampled at RESET, and a signal name in parenthesis "( )" represents a strobed mode signal.
Table 1-4_ Pentium™ Processor/MBC Interface Signals
APCHK# ClK HOLD INTR PEN# SMIACT#
BP[3:2],PM/BP[1 :0) FERR# IBT IU PRDY TCK
BRDY#
FlUSH# IERR# IV
RIS#
TOI
BREQ HlDA IGNNE# NMI RESET TOO
BUSCHK# HIT# INIT
PCHK# SMI# TMS
TRST#
1-14
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