Mcyc - Intel 82496 CACHE CONTROLLER User Manual

HARDWARE INTERFACE
5.2.2.88. MCYC#
MCYC# Memory Bus Cycle
Indicates that the current cycle will use the memory buffers.
Output from 82496 Cache Controller (pin 018), Input to 82491 Cache SRAM (pin
42)
Synchronous to ClK
Signal Description
MCYC# is a one CLK pulse and, when sampled by the 82491 Cache SRAM, latches the
current cycle address into one of the memory cycle address buffers. It selects which memory
cycle address buffer will provide the array address, and allocates a memory cycle data buffer
for the upcoming memory bus cycle.
Relation to Other Signals
None.
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