Cache Synchronization; Mesi State Changes Following Cycles With Special Attributes; Cacheability Attributes: Pcd, Mken; Write Through Protocol: Pwt, Mwb/Wt - Intel 82496 CACHE CONTROLLER User Manual

COMPONENT OPERATION
3.5.2.2.
CACHE SYNCHRONIZATION
Cache synchronization is performed to make main memory consistent with the 82496 Cache
Controller/82491 Cache SRAM. FLUSH and SYNC are used to maintain cache
synchronization.
A cache flush is initiated by asserting the FLUSH# pin. Once this operation is initiated, the
82496 Cache Controller/82491 Cache SRAM writes all [M] lines out to main memory and
performs processor inquires and back-invalidation cycles. Subsequently, aU Pentium processor
cache and 82496 Cache Controller/82491 Cache SRAM entries are in the [I] state.
Cache synchronization is initiated by asserting the SYNC# pin. Once the operation is initiated,
the 82496 Cache Controller/82491 Cache SRAM writes all [M] lines out to main memory and
performs processor inquires. Subsequently, all Pentium processor cache and 82496 Cache
Controller/82491 Cache SRAM entries are in a non-modified state (E, S, or I).
3.6. MESI STATE CHANGES FOLLOWING CYCLES WITH
SPECIAL ATTRIBUTES
3.6.1. Cacheability Attributes: PCD, MKEN#
The 82496 Cache Controller/82491 Cache SRAM allows cacheability to be determined on a
page basis as well as on a line basis. Page cache ability is implemented in the CPU by
initialization of the page table so that it drives the PCD output appropriately. The memory bus
controller implements line by line cacheability by asserting the MKEN# signal.
The Page Caching Disabled attribute is driven by the processor's PCD output and corresponds
to a cacheability bit in the page table entry of a memory location's virtual address. If the PCD
bit is asserted when the CPU presents a memory address, the memory location will not be
cached in the 82496 Cache Controller/82491 Cache SRAM or the CPU.
MKEN# is a 82496 Cache Controller input which connects to the memory bus controller or to
the bus itself. When MKEN# is inactive, it prevents a memory location from being cached in
the 82496 Cache Controller/82491 Cache SRAM and the CPU. MKEN# affects only the
current access.
If the PCD output or MKEN# input render a read miss non-cacheable, the line will not be
cached in the 82496 Cache Controller/82491 Cache SRAM or the CPU cache, leaving cache
state information unaltered. On a write miss, a non-cache able indication from either input
initiates a write miss without allocation. PCD has no effect on read hit cycles if the 82496
Cache Controller/82491 Cache SRAM already has a valid copy of a given line.
3.6.2. Write Through Protocol: PWT, MWB/WT#
The 82496 Cache Controller/82491 Cache SRAM allows write-through protocol to be
implemented on a page basis as well as on a line basis. Write through policy is selected for a
particular line by either using the PWT attribute in the CPU page table or driving the
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