Signal Interconnects On Optimized Interface - Intel 82496 CACHE CONTROLLER User Manual

PINOUTS
Table 1-14.
Signal Interconnects
on Optimized Interface (Contd.)
Pentium™ Processor 82496 Cache Controller
82491 Cache SRAM
HITM#
(0)
HITM# (I) HITM# (I)
INV (I) INV(O)
KEN#(I) KEN#
(0)
LOCK# (0) LOCK# (I)
M/IO# (0)
M/IO# (I)
MAWEA# (0) MAWEA# (I)
MCYC#(O) MCYC#(I)
NA# (I) NA#
(0)
PCD
(0)
PCD (I)
PWT (0)
PWT(I)
SCYC
(0)
SCYC (I)
W/R# (0)
W/R#(I) W/R# (I)
WAY
(0)
WAY (I)
WBIWT#(I) WBIWT#(O)
WBA [SEC2#]
(0)
WBA [SEC2#] (I)
WBTYP [LRO]
(0)
WBTYP [LRO] (I)
WBWE# [LR1] (0) WBWE# [LR1] (I)
WRARR#
(0)
WRARR#(I)
• The Pentium processor Byte Enable outputs are connected to 82491 Cache SRAM CDATA[7:4] pins
for 82491 Cache SRAM s configured to be data parity devices. The Pentium processor Data Parity
signals are connected to 82491 Cache SRAM CDATA[3:0] pins for 82491 Cache SRAM s configured to
be parity devices.
1-38
I