Line Ratio; Tagram Size; Tagram Structure - Intel 82496 CACHE CONTROLLER User Manual

CACHE INITIALIZATION AND CONFIGURATION
4.2.2.
Line Ratio
Line Ratio (LR) is the ratio between the 82496 Cache Controller/82491 Cache SRAM line size
and that of the Pentium processor. If LR=2, for example, the 82496 Cache Controller/82491
Cache SRAM second-level cache line size is 64 bytes. Along with the bus width, the LR
determines the number of transfers needed to fill a 82496 Cache Controller/82491 Cache
SRAM cache line. Only one line is filled on each line fill cycle, regardless of sectoring. The
LR is used to determine the number of inquires and back invalidations to the CPU.
4.2.3.
TagRAM Size
The 82496 Cache Controller/82491 Cache SRAM tagRAM size can be configured with 4K or
8K tag entries. By reducing tagRAM size, the LR can be doubled without a change in cache
size. TagRAM size is actually determined when selecting cache line size and bus width.
4.2.4.
TagRAM Structure
Because there are many more lines in main memory than line locations in the cache, the 82496
Cache Controller uses address mapping. Given a physical address in main memory, mapping
finds the cache location that contains the corresponding data. The 82496 Cache Controller
uses a two-way set associative tagRAM address mapping mechanism (see Figure 4-4).
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