Inv - Intel 82496 CACHE CONTROLLER User Manual

HARDWARE INTERFACE
5.2.2.64. INV
INV
Pentium processor Cache Invalidation Request
Indicates a request to invalidate the CPU cache line.
Output from 82496 Cache Controller (pin l16), Input to Pentium processor (pin
A01)
Synchronous to ClK
Signal Description
INV is a 82496 Cache Controller output which indicates a request to force the Pentium
processor cache line to an invalid state if the inquire or back-invalidation hits the first level
cache.
INV is driven active to the CPU when SNPINV is sampled active by the 82496 Cache
Controller and during replacements of modified lines in the 82496 Cache Controller/82491
Cache SRAM cache (for example, when a replacement occurs as a result of a linefill).
When Driven
INV is driven to a valid level by the 82496 Cache Controller in the same CLK as EADS# and
is a "don't care" at all other times.
Relation to Other Signals
Pin Symbol Relation to Other Signals
EADS#
INV is driven with EADS# to the CPU.
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