Basic Mesi State Transitions - Intel 82496 CACHE CONTROLLER User Manual

[I] - INVALID
COMPONENT OPERATION
The [I] state indicates that a particular line is not available in the
cache. A read to this line results in a miss, which, in some cases,
causes the 82496 Cache Controller to execute a line fill. A write to
this line causes the 82496 Cache Controller/82491 Cache SRAM to
execute a write-through to main memory or, in some circumstances,
to initiate an allocation.
3_5. BASIC MESI STATE TRANSITIONS
The MESI state of a cache line depends on several factors, including CPU cycle type and
memory bus controller operation. Following a snoop, the MESI state of a line may change, or
the line may be written back.
This section covers the most common memory accesses. Non-cacheable cycles, locked cycles,
read-only cycles, and direct-to-modified cycles are covered in Section 3.6.
One category of memory accesses deals with MESI state changes to the CPU-cache core
resulting from internal operations. Another category deals with MESI state changes resulting
from actions by external devices. Figure 3-1 diagrams a portion of the MESI coherency
protocol. The diagram shows state transitions caused by both categories of memory accesses.
Table 3-1 below shows the basic MESI state transitions implemented by the 82496 Cache
Controller/82491 Cache SRAM. The "CURRENT STATE" refers to the state of the 82496 Cache
Controller/82491 Cache SRAM line being accessed either by it's Pentium processor or a snoop
from another cache on the memory bus. The "ACTION" refers either to a CPU read, CPU write,
or a snoop initiated by another bus master attached to the same shared memory bus. The "NEW
STATE" refers to the state of the current cache line after the action is performed. The new state
is dependent upon the values of SNPINV and SNPNCA for snoop operations, and DRCTM#,
MWB/WT#, LOCK#, MKEN#, and MRO# for read and write operations. "MEMORY Bus
ACTIVITY" refers to the action which takes place on the memory bus (if any) as a result of the
action being performed on the cache line.
I
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