Intel 82496 CACHE CONTROLLER User Manual page 263

HARDWARE INTERFACE
Relation to Other Signals
Pin Symbol
Relation to Other Signals
CADS# Address and cycle specification signals (i.e., APIC#, CCACHE#,
CD/C#,
CM/IO#,
CPCD, CPWT, CSCYC,
CW/R#,
CWAY, KLOCK#, MAP, MBT[3:0], MCACHE#,
MCFA, MSET, MTAG, NENE#, PALLC#, RDYSRC, and SMLN#) are valid with
CADS#.
BT[3:0] The MBT[3:0] outputs of the cache controller reflect the BT[3:0] inputs during
Branch Trace Message Special Cycles.
IBT (Pentium If TR12.TR (bit 1 in Test Register 12 of Pentium processor) is set to 1, MBT[3:0]
processor signal) are driven along with the branch trace message special cycle for each assertion of
IBT.
5-138
I