Cache Memory Considerations - Intel PXA255 User Manual

Optimization Guide
A.4.4.6.

Cache Memory Considerations

Stride, the way data structures are walked through, can affect the temporal quality of the data and
reduce or increase cache conflicts. The Intel® XScale™ core data cache and mini-data caches each
have 32 sets of 32 bytes. This means that each cache line in a set is on a modular 1K-address
boundary. The caution is to choose data structure sizes and stride requirements that do not
overwhelm a given set causing conflicts and increased register pressure. Register pressure can be
increased because additional registers are required to track prefetch addresses. The effects can be
affected by rearranging data structure components to use more parallel accesses to search and
compare elements. Similarly rearranging sections of data structures so that sections often written fit
in the same half cache line [16 bytes for the Intel® XScale™ core] can reduce cache eviction write-
backs. On a global scale, techniques such as array merging can enhance the spatial locality of the
data.
As an example of array merging, consider the following code:
int a [NMAX];
int b [NMAX];
int ix;
for (i=0; i<NMAX]; i++)
{
ix = b[i];
if (a[i] != 0)
ix = a[i];
do_other calculations;
}
In the above code, data is read from both arrays a and b, but a and b are not spatially close. Array
merging can place a and b spatially close.
struct {
int a;
int b;
} c_arrays;
int ix;
for (i=0; i<NMAX]; i++)
{
ix = c[i].b;
if (c[i].a != 0)
ix = c[i].a;
do_other_calculations;
}
As an example of rearranging often written arrays to sections in a structure, consider the code
sample:
struct employee
struct employee *prev;
struct employee *next;
float Year2DatePay;
float Year2DateTax;
int ssno;
int empid;
float Year2Date401KDed;
float Year2DateOtherDed;
};
In the data structure shown above, the fields Year2DatePay, Year2DateTax, Year2Date401KDed,
and Year2DateOtherDed are likely to change with each pay check. The remaining fields however
change very rarely. If the fields are laid out as shown above, assuming that the structure is aligned
A-20
{
Intel® XScale™ Microarchitecture User's Manual