Cache Size; Configurable Address Connections - Intel 82496 CACHE CONTROLLER User Manual

CACHE INITIALIZATION AND CONFIGURATION
are modified.
4.2.6.
Cache Size
The 82496 Cache Controller/82491 Cache SRAM may be configured as 256K or 512K bytes
in size. Cache size is directly proportional to the number of 82491 Cache SRAM devices used.
Eight components comprise a 256K cache, while 16 can be combined to construct a 512K
cache. Two 82491 Cache SRAM devices can be added to each cache size and configured to be
data parity devices.
4.2.7.
Configurable Address Connections
Table 4-3 lists which address lines should be connected to each of the CFA[6:0] lines for each
cache configuration. CFA[6:0] provide the 82496 Cache Controller with proper multiplexed
addresses for each of the possible cache configurations. They may be used as set addresses (S),
tag addresses (T), line in sector address (L), 82496 Cache Controller subline address (CL), or
CPU subline address (CS), and are passed along to the memory bus.
Table 4-3. Pentium™ Processor CFA Address Connections
Config
TAG SET
Number
CFA6 CFA5 CFA4 CFA3 CFA2 CFA[1:0] [11 :0]
[10:0]
1
A5(S) VSS A31(T) A30(T) A29(T) A[4:3](CS) A[28:17] A[16:6]
2 A5(CL) VSS A31(T) A30(T) A29(T) A[4:3](CS) A[28:17] A[16:6]
3 A6(S) A5(L) VSS A31 (T) A30(T) A[4:3](CS) A[29:18] A[17:7]
4
A6(S) A5(CL) VSS A31 (T) A30(T) A[4:3](CS) A[29:18] A[17:7]
5 A6(CL) A5(CL) VSS A31 (T) A30(T) A[4:3](CS) A[29:18] A[17:7]
The memory address bus signals, MCFA[6:0], correspond directly to the sequence in which
the CPU address bus signals, CFA[6:0], are connected. In the cases where the CPU address
signals are connected directly to VSS, the memory address signals must be left as no-connects
(NC). Therefore, in configurations 1 and 2, MCFA5 is an NC and in configurations 3,4, and 5,
MCFA4 is an NC.
The 82496 Cache Controller memory address bus is controlled by four inputs: MALE and
MBALE address latch enables, and MAOE# and MBAOE# address output enables. MALE and
MAOE# control the 82496 Cache Controller line address signals (S,T,L), and MBALE and
MBAOE# control the subline address signal
(CL,~S).
Table 4-4 describes which memory bus
address signals are controlled by each of the above address control signals. Figure 4-5 shows
the line and subline address latches.
I
4-7