Intel 82496 CACHE CONTROLLER User Manual page 367

MEMORY BUS FUNCTIONAL DESCRIPTION
Figure 6-10 illustrates I/O write (cycle A) and read (cycle B) accesses. An I/O write is the only
write cycle that is not posted by the 82496 Cache Controller, i.e. the cycle is not fully acknowl-
edged to the CPU until it is completed on the memory bus.
In clock 1, the Pentium processor issues an ADS# of an I/O write cycle. In clock 3 the 82496
Cache Controller issues CADS# (also CDTS#) with all cycle control signals. RDYSRC is high
indicating the MBC to supply BRDY#s to the CPU. The MBC activates BRDY# (clock 8) to
both the 82496 Cache Controller and the CPU. CRDY# is activated in clock 9 indicating to the
82496 Cache Controller the completion of the cycle on the memory bus. The 82496 Cache
Controller can pipeline I/O cycles, i.e CNA# is recognized during all I/O cycles. Note that
BLEC# is activated either after CNA# (cycle A, clock 7), or after CRDY# (cycle B, clock 14).
In clock 4, the CPU issues an ADS# of an I/O read cycle. This cycle is similar to non-
cacheable read miss cycles with burst length
=
1, i.e CACHE# is high. Upon completing the
access on the memory bus, the MBC activates BRDY# (since RDYSRC is high) and CRDY#.
Note that BRDY# of a cycle may come before (cycle A), with (cycle B), or after the CRDY#
of the same cycle.
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