Ken - Intel 82496 CACHE CONTROLLER User Manual

HARDWARE INTERFACE
5.2.2.68.
KEN#
KEN# Cache Enable
Indicates the cacheability of the cycle to the CPU.
Output from 82496 Cache Controller (pin E17), Input to Pentium processor (pin
J03)
Synchronous to ClK
Signal Description
This is the cache enable pin. It is used to indicate to the Pentium processor that the current
cycle is cache able or not. KEN# is an output of the 82496 Cache Controller and is connected to
the Pentium processor KEN# input. KEN# is normally active and will be deactivated as a
function of MKEN# (memory bus cacheability), MRO# (memory bus read only), and D/C#
(data or code). KEN# is also determined by the values of CACHE# and LOCK# from the CPU.
When Driven
KEN# is valid with either NA# or the first BRDY# of the cycle (whichever comes first).
Table 5-6 summarizes the cases when KEN# is active and inactive.
Table 5-6. KEN# Operation
Cycle Type KEN# Note
locked cycles 1 3
1/0
x
Memory Write
x
Pentium™ processor Non-Cacheable (CACHE#=1) cycles 1 3
Non Cacheable Read Miss
x
Cacheable Code Read Miss
0
1
Cacheable Code Read Hit 0
Cacheable Data Read Miss (MRO# sampled inactive) 0 1
Cacheable Data Read Miss (MRO# sampled active) 1 1
Cacheable Data Read Hit (TRO inactive)
0 2
Cacheable Data Read Hit (TRO active) 1 2
NOTES:
1. MKEN# sampled active. If MKEN# is sampled inactive, KEN# will be driven inactive for all cases.
2. TRO = 82496 Cache Controller tag RAM Read Only bit.
3. KEN# will be returned inactive for any cycle in which the 82496 Cache Controller samples CACHE#
inactive (i.e. locked and Pentium processor non-cacheable cycles)
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