Mesi State Changes Resulting From Memory Bus Masters; Snooping - Intel 82496 CACHE CONTROLLER User Manual

COMPONENT OPERATION
allocation (linefill).
The allocation can be performed pending the following circumstances:
• The write is cacheable (active MKEN#)
• PCD and PWT are not asserted
• The write is not LOCKed
• The write is to memory, not to I/O
• The write is a miss, not a hit
3.5.2.
MESI State Changes Resulting From Memory Bus Masters
MESI state transitions within the 82496 Cache Controller/82491 Cache SRAM may result
from the activities of other processing units within the shared memory system.
The device in control of the bus at any time is called the bus master. When the 82496 Cache
Controller/82491 Cache SRAM is not in control of the bus during snoop operations, it is
referred to as the "slave".
3.5.2.1.
SNOOPING
In snoop operations, the bus master requests the slaves to examine their cache lines for the data
that the bus master is requesting from main memory. A "snoop hit" occurs when one of the
slaves contains this memory information, whether it be modified or not.
There are three primary purposes of snooping:
1. Requesting modified data from other caches.
2. Invalidating data in other caches in the case of write cycles.
3. Sharing data between caches.
How the slave enacts MESI state changes following a snoop hit depends on the SNPINV and
SNPNCA input attributes driven by the bus master.
The SNPINV input directs a slave to invalidate a snooped line since the bus master contains
the most recent version of the data. The snooped line is placed in the [I] state.A back-
invalidation procedure is initiated to instruct the slave CPU to invalidate any copy of the data
that it might also contain. For example, if a bus master performs a write cycle to memory, the
slave memory bus controller must snoop and assert SNPINV since its copy will no longer be
consistent with memory.
When asserted, the SNPNCA input indicates to a slave that the requesting master is performing
a non-cacheable read. A snoop hit to an [M] or [E] line can be placed in the [E] state because
the bus master will not cache the line.
If
SNPNCA is not asserted, the bus master will cache the
line. The cache line must be placed in the [S] state to ensure that a future write hit invalidates
the line in other caches. Regardless of SNPNCA, an [S] line remains in the [S] state following
a snoop hit. In addition, when SNPINV is asserted, it always overrides SNPNCA.
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