Brdy - Intel 82496 CACHE CONTROLLER User Manual

HARDWARE INTERFACE
5.2.2.17. BRDY#
BRDY# Burst Ready
Burst ready input.
Input to Pentium processor (pin l04), 82496 Cache Controller (pin 002), and
82491 Cache SRAM (pin 60)
Synchronous to ClK
Signal Description
BRDY# is an MBC output to the Pentium processor, 82496 Cache Controller cache controller,
and 82491 Cache SRAM cache memories. In the CPU, BRDY# provides the BRDY# function
described in the Pentium processor DATA BOOK. In the 82491 Cache SRAM memories,
BRDY# increments the CPU latch burst counter.
During CPU initiated memory bus read cycles, BRDY# advances the 82491 Cache SRAM
CPU latch burst counter to allow the next 64-bit read data slice to be available on the CPU data
bus. At the same time, BRDY# latches the previous data slice into the CPU.
With the exception of I/O cycles, BRDY# is not needed during writes because the cache posts
CPU write cycles.
During special CPU cycles and I/O cycles, BRDY# is used to end the CPU cycle.
BRDY# must not be asserted until the bus is granted (until BGT# is asserted) and until the data
path is ready for transfers (until data is valid-CDTS# is asserted).
When Sampled
BRDY# is sampled by the CPU, 82496 Cache Controller and 82491 Cache SRAM at every
CLK edge. BRDY# must always meet proper set-up and hold times. BRDY# assertion
advances the CPU latch counter in the 82491 Cache SRAM even when the CPU latch is not in
use.
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