Intel 82496 CACHE CONTROLLER User Manual page 45

PINOUTS
Table 1-10. Pentium™ Processor CPU-Cache Chip Set Brief Pin Descriptions (Contd.)
Symbol
Type
Part Name and Function
IU
0
P The U-Pipe Instruction Complete signal is driven active (high) for 1 clock
to indicate that an instruction in the u-pipeline has completed execution.
This pin is always driven by the Pentium processor.
IV
0
P The V-Pipe Instruction Complete signal is driven active (high) for one
clock to indicate that an instruction in the v-pipeline has completed
execution. This pin is always driven by the Pentium processor.
KEN#
0
CC The Cache Enable pin is used to determine whether the current cycle is
I P
cacheable by the CPU or not and is, consequently, used to determine
cycle length. When the Pentium processor generates a cycle that can be
cached (CACHE# asserted) and KEN# is returned active by the 82496
Cache Controller, the cycle will be transformed into a burst line fill cycle.
KLOCK#
0
CC 82496 Cache Controller Cache LOCK# is driven by the 82496 Cache
Controller and indicates to the memory bus controller that a request to
execute atomic read-modify-write sequences is present. KLOCK# tracks
the LOCK# signal of the Pentium processor.
KWEND# I CC Cacheability Window End is generated by the MBC to indicate to the
82496 Cache Controller that the Cacheability Window (the period during
which cacheability is determined) has expired. When KWEND# is as-
serted, the 82496 Cache Controller latches the memory cacheability
signal (MKEN#) and the Memory Read-Only Signal (MRO#), and makes
determinations based on the cacheability attributes (e.g. whether a line is
cacheable, is read-only, requires a replacement, or requires an allocation).
KWEND# shares a pin with the Configuration signal CFG2.
LOCK#
I CC
The Bus Lock pin indicates that the current bus cycle is locked. The
0
P Pentium processor will not allow a bus hold when LOCK# is asserted (but
AHOLD and BOFF# are allowed). LOCK# goes active in the first clock of
the first locked bus cycle and goes inactive after the BRDY# is returned for
the last locked bus cycle. LOCK# is guaranteed to be deasserted for at
least one clock between back to back locked cycles. The LOCK# pin is
driven to the 82496 Cache Controller which, in turn, drives the memory
bus KLOCK# output.
LR[1:0]
0
CC The Line Ratio 1 and 0 Optimized Interface Configuration signals are
I
CS
driven by the 82496 Cache Controller to the 82491 Cache SRAM at
RESET to pass along line ratio information.
LR1 shares pins with the 82496 Cache Controller and 82491 Cache
SRAM WBWE# signals.
LRO shares pins with the 82496 Cache Controller and 82491 Cache
SRAM WBTYP signals.
M/IO#
I CC
The Memory/Input-Output signal is one of the primary bus cycle
0
P definition pins. It is driven valid in the same clock as the ADS# signal is
asserted. M/IO# distinguishes between memory and I/O cycles.
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