Intel 82496 CACHE CONTROLLER User Manual page 140

HARDWARE INTERFACE
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Figure 5-7. 82496 Cache Controller Snooping Operations
To initiate a snoop, the MBC asserts SNPSTB#, which latches snoop information into the
82496 Cache Controller. The 82496 Cache Controller synchronizes this information, if
necessary, and generates the snoop cycle signal (SNPCYC#) to indicate that snooping is taking
place. SNPCYC# may be delayed by synchronization and/or snoop blocking. SNPCYC#
indicates to the MBC that it may read the 82496 Cache Controller's snoop responses on the
next CLK.
If the 82496 Cache Controller/8249l Cache SRAM needs to write back a modified line or is
already performing a back-invalidation, the Snoop Busy signal (SNPBSY#) is asserted.
SNPBSY# indicates that the 82496 Cache Controller can accept another snoop request (once
SNPCYC# is asserted), but will not service that snoop until after SNPBSY# goes inactive.
Once SNPCYC# is asserted, the 82496 Cache Controller's snoop latch can accept another
snoop request. As a result, snoops may be pipelined. Figures 5-8 and 5-9 show the fastest
synchronous and asynchronous snooping possible. Note that the MBC must not assert
SNPSTB# for a new snoop operation until it has sampled SNPCYC# active for the first snoop
operation (refer to section 5.1.2.4). Note that, during asynchronous snooping, the SNPSTB#
for the following snoop can only occur after the falling edge of the SNPCYC# of the previous
snoop.
The 82496 Cache Controller responds after a snoop look up by driving the MHITM# and
MTHIT# signals after the clock in which SNPCYC# is asserted. MHITM# is asserted for
snoop hits to an [M] state line. MTHIT# is asserted for snoop hits to [M],[E], .and [S] state
lines. These signals indicate the state of the 82496 Cache Controller line just prior to the snoop
operation.
The MBC can predict the final state of the 82496 Cache Controller line by knowing the initial
state and the values of the SNPINV and SNPNCA signals during the snoop operation. Figures
5-10 and 5-11 show the 82496 Cache Controller response to snoops without and with
invalidation, respectively.
MHITM#, MTHIT#, SNPCYC#, and SNPBSY# are all synchronous to CLK.
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