Wwor - Intel 82496 CACHE CONTROLLER User Manual

HARDWARE INTERFACE
5.2.2.148. WWOR#
WWOR# Weak Write Ordering Mode
Enforces strong/weak write-ordering policy.
Configuration input to 82496 Cache Controller (pin R03)
Synchronous to ClK
Signal Description
When WWOR# is asserted during RESET, the 82496 Cache Controller enforces a weak write-
ordering policy. If WWOR# is de-asserted during RESET, the 82496 Cache Controller
enforces a strong write-ordering policy.
In strong write-ordering mode, memory bus writes occur in the order in which they were given
by the CPU. In weak write-ordering mode, the following situation can arise:
1.
A data from CPU posted write (Write A) resides in an 82491 Cache SRAM memory buffer
2. A subsequent CPU write (Write B) completes in the 82496 Cache Controller/82491 Cache
SRAM's second-level cache because of a cache hit to a line in the [M] or [E] state
3. A snoop hit to B causes a write-back of the modified line from Write B before the line
from Write A is written back.
Here, the line modified by Write B is written to memory before the data from Write A, causing
a re-ordering of CPU writes. This scenario creates a potential operating system problem if
Write A writes to a location locked by a semaphore which Write B unlocks prematurely.
The reordering does not take place if Write B unlocks the semaphore using a read-modify-
write sequence.
When Sampled
WWOR# is sampled during RESET as shown in the Initialization and Configuration chapter.
Following the falling edge of RESET, WWOR# becomes the MALE input.
Relation to Other Signals
Pin Symbol
Relation to Other Signals
RESET WWOR# is sampled when RESET is
~ctive.
Refer to Chapter 4 for specific timing
requirements with respect to RESET.
EWBE#
If the 82496 Cache Controller is configured in the weak write ordering mode,
EWBE# is always driven active to the CPU.
MALE WWOR# shares a pin with MALE.
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