Fsiout - Intel 82496 CACHE CONTROLLER User Manual

HARDWARE INTERFACE
5.2.2.53. FSIOUT#
FSIOUT# Flush,
Sync,
Initialization
Indicates beginning/end of Flush, Sync, Initialization (including self test)
operations.
Output from 82496 Cache Controller (pin E02)
Synchronous to ClK
Signal Description
This signal indicates the start and the end of a flush, sync or initialization operations (including
self-test, if requested). These operations are never active simultaneously. The signal is
activated when one of the three operations begins, and goes inactive when the operation is
complete.
FSIOUT# active indicates that either Flush, Sync or Initialization operation is in progress.
Only one of these operations can take place at a time in the 82496 Cache Controller. Table 5-4
shows the priorities of these three operations.
Table
5-4.
FSIOUT#
Operation Priorities
Operation Initiating Signal Priority
Initialization
RESET Highest
Flush
FLUSH#
Sync
SYNC# lowest
If a signal of Higher priority is asserted while a lower priority operation is in progress, then the
lower priority operation is aborted and the higher priority operation is executed. If a signal of
lower priority is asserted when a higher priority operation is taking place, the lower priority
signal is ignored. Once a FLUSH# or SYNC# operation has begun, its trigger signal is ignored
until the operation completes.
When a higher priority operation aborts a lower priority one, FSIOUT# remains active.
When Driven
This signal is asserted whenever a flush, sync or initialization operation is internally
recognized by the 82496 Cache Controller.
FSIOUT# remains asserted until the end of the flush, sync or initialization operation. It is
deasserted after the last line is handled. If the last line is a hit to [M], then FSIOUT# is
deasserted after the CRDY# of the write back.
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