Boff - Intel 82496 CACHE CONTROLLER User Manual

HARDWARE INTERFACE
5.2.2.15.
BOFF#
BOFF# Back Off
Prevents CPU bus deadlock by aborting outstanding Pentium processor cycles.
Output from 82496 Cache Controller (pin H16), Input to Pentium processor (pin
K04) and 82491 Cache SRAM (pin 36)
Synchronous to ClK
82491 Cache SRAM internal Pull-up
Signal Description
This signal is an input to the Pentium processor and gives the 82496 Cache Controller the
capability to abort a CPU cycle when required. The 82496 Cache Controller will only activate
BOFF# during situations where a deadlock exists (e.g., CPU miss cycle, 82496 Cache
Controller inquire cycle: deadlock on usage of the CPU bus). BOFF#, when asserted, allows
the 82496 Cache Controller to prevent CPU bus deadlock by causing the Pentium processor to
abort the current cycle and float its bus.
BOFF# is also an input to the 82491 Cache SRAMs and, when active, causes the SRAMs to
clear their CPU bus cycle information since the current CPU bus cycle will be aborted.
Activity on the memory bus (i.e., a posted write) will continue without interruption.
When Driven
BOFF# is driven when an inquire to the Pentium processor hits a line in [M] state, and there is
an outstanding cycle that cannot be completed (cannot receive its last BRDY# or BRDYC#).
The BOFF# signal will be driven for 1 CLK only.
Relation to Other Signals
None.
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