Intel 82496 CACHE CONTROLLER User Manual page 288

HARDWARE INTERFACE
5.2.2.101. MSTBM
MSTBM Memory Strobed Mode
Strobed memory mode selection.
Configuration input to 82491 Cache SRAM (pin 26)
Synchronous to ClK
Signal Description
MSTBM determines whether the 82491 Cache SRAM operates in the strobed memory bus
mode or in clocked memory bus mode. If MSTBM is sampled (tied) HIGH or LOW on and
after the falling edge of RESET, the 82491 Cache SRAM operates in strobed mode. If a CLK
is detected on this pin any time after the falling edge of RESET, the 82491 Cache SRAM
enters clocked memory bus mode, and the input becomes the memory CLK (MCLK) input.
When Sampled
MSTBM is sampled as shown in the Initialization and Configuration chapter.
Relation to Other Signals
Pin Symbol Relation to Other Signals
RESET
MSTBM is sampled when RESET is active. Refer to Chapter 4 for specific timing
requirements with respect to RESET.
MClK In clocked memory bus mode, MSTBM is connected to the MClK source to
become the MClK input.
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