Main Features; Cpu/Cache Core Description; 82496 Cache Controller - Intel 82496 CACHE CONTROLLER User Manual

CACHE ARCHITECTURE OVERVIEW
2.1. MAIN FEATURES
The 82496 Cache Controller/82491 Cache SRAM have the following main fetaures:
• Tracking of Pentium processor speed
• Large Cache Size support:
4K or 8K Tags
1 or 2 lines per sector
4 or 8 transactions per line
64 or 128-bit wide configurable memory bus
elementary 32-bit memory bus implementation
256K or 512K byte cache
• Write-Back cache design with full multiprocessing consistency support:
supports the MESI protocol
monitors memory bus to ensure cache consistency
maintains inclusion with CPU cache
may be used as a write-through cache
allows write-allocations
• Two-way set-associative with MRU hit prediction and replacement algorithm
• Zero wait-state read hit cycles on MRU hit. One wait-state read hit on MRU misses
• Zero wait-state write hit cycles
• Concurrent CPU and Memory Bus transactions
• Support of synchronous, asynchronous, and strobed memory bus architectures
• Support of write posting
• Support of weak or strong memory write ordering
• Address parity checking and error notification on CPU and memory bus
• Internal tagRAM and address path parity checking and error notification
• Data parity storage and transfer to CPU bus via 82491 Cache SRAM parity devices
2.2. CPU/CACHE CORE DESCRIPTION
2.2.1. 82496 Cache Controller
The 82496 Cache Controller is the main control unit for the 82496 Cache Controller/82491
Cache SRAM second-level cache subsystem (see Figure 2-1). The 82496 Cache Controller
contains tags, line states, and read-only information, and determines cache hits and misses. The
controller handles all CPU request traffic including requests for memory bus access. The
2-2 I