Read Miss Cycles; With Clean Replacement - Intel 82496 CACHE CONTROLLER User Manual

MEMORY BUS FUNCTIONAL DESCRIPTION
6.1.2.
Read
Miss Cycles
6.1.2.1. WITH CLEAN REPLACEMENT
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memory bus.
MClK is asynchronous to ClK
Figure 6-2. Read Miss With Clean Replacement
Figure 6-2 illustrates CPU read cycles (A, B) that miss the 82496 Cache Controller. In such
cycles, the 82496 Cache Controller will instruct the MBC (memory bus controller) to perform
a cache line-fill cycle on the memory bus (a cache line-fill is a read of a complete 82496 Cache
Controller line from the main memory). The line is then written into the 82491 Cache SRAM
ARRAY, and data transferred to the CPU as requested). If the line fetched from the main
memory replaces a valid unmodified line (i.e. [E] or [S]), then a back-invalidation cycle is
6-4
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