Intel 82496 CACHE CONTROLLER User Manual page 295

HARDWARE INTERFACE
5.2.2.107. NA#
NA# Next Address
Indicates that a new address cycle can be generated.
Output from 82496 Cache Controller (pin K18), Input to Pentium processor (pin
K03)
Synchronous to ClK
82496 Cache Controller internal Pull-up
Signal Description
Prior to the 82496 Cache Controller issuing NA# to the Pentium processor, it must insure the
following rules:
1. Pipelining is no more than 1.5 deep. This means that no more than two active ADS# cycles
are allowed. Therefore, an NA# for a subsequent cycle cannot be issued until the
BRDY#.BLAST# or BRDYC#*BLAST# of the fIrst outstanding ADS# cycle has been
driven.
2. The CPU Byte Enables (BE[7:0]#) for the current ADS# has been latched in the 82491
Cache SRAM Byte Enable Latch (MBE#). Refer to the BLEC# and MBE# signal
descriptions for details.
3. The caching attributes (KEN# and WB/WT#) to the Pentium processor are known or not
sampled.
For cycles which sample KWEND# (MKEN#&MRO#), the caching attributes are known one
CLK after KWEND#. For cycles which do not sample KWEND#, the caching attributes may
be known earlier. An NA# that is driven when the caching attributes are not sampled is called a
'Blind NA#'. A Blind NA# has the advantage of potentially being as early as one CLK after
ADS#.
A Blind NA# is issued in the following cases:
1. Locked cycles. The caching attributes do not apply since the cycles are not CPU
cacheable.
2. Write cycles. The caching attributes are available as early as one CLK after ADS#.
3. Read cycles which are not cacheable in the CPU (CACHE# is inactive). The caching
attributes are not sampled.
When Driven
For non-cacheable hit cycles, a Blind NA# will be issued.
For non-cacheable miss cycles, NA# will be issued once the CPU Byte Enables are latched
(using BLEC#).
For cacheable miss cycles, NA# will be issued one CLK after KWEND#. Note that since it is a
miss to the 82496 Cache Controller/82491 Cache SRAM cache WB/WT# will always be
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