Snoop Modes; Synchronous Snoop Mode; Clocked (Asynchronous) Snoop Mode; Strobed Snoop Mode - Intel 82496 CACHE CONTROLLER User Manual

CACHE ARCHITECTURE OVERVIEW
• 256-Kbyte or 512-Kbyte cache
• 64 or 128 bit wide memory bus
• One or two lines per sector
• 1:1,1:2, or 1:4 CPU to 82496 Cache Controller line size ratio
• 4 or 8 memory bus transactions
• 4K or 8K tag size
• Strong/weak write ordering
2.3.2. Snoop Modes
When another master snoops the 82496 Cache Controller, the MBC must initiate the snoop
request and pass on the 82496 Cache Controller response. The 82496 Cache Controller allows
the MBC to initiate this snoop request in one of three modes: synchronous, clocked
(asynchronous), and strobed. The snoop response of the 82496 Cache Controller is always
synchronous.
2.3.2.1.
SYNCHRONOUS SNOOP MODE
When the MBC initiates the snoop in synchronous snoop mode, the 82496 Cache Controller
latches all snoop information synchronous to the CPU CLK. The snoop is then performed on
the next CLK edge (if resources are available). The snoop response is given on the CLK edge
after the snoop is performed. This is the fastest possible method of snooping.
2.3.2.2.
CLOCKED (ASYNCHRONOUS) SNOOP MODE
In clocked (asynchronous) snooping mode, the 82496 Cache Controller latches snoop
information with respect to an external snoop clock (SNPCLK). SNPCLK frequency is slower
than CLK frequency. The 82496 Cache Controller must internally synchronize this information
to CLK and provide a response. .
2.3.2.3.
STROBED SNOOP MODE
In strobed snooping mode, the 82496 Cache Controller latches snoop information with respect
to the falling edge of SNPSTB#. Thus, snoop initiation is clock independent. The 82496 Cache
Controller again synchronizes this snoop information with CLK.
2.3.3. Memory Bus Modes
The 82491 Cache SRAM may be configured in one of two memory bus modes: clocked mode
and strobed mode. The memory bus mode determines how data will be passed on t%ff of the
data bus. The memory bus mode is not related to the snoop mode.
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