Bgt - Intel 82496 CACHE CONTROLLER User Manual

HARDWARE INTERFACE
5.2.2.11.
BGT#
BGT#
Bus Guaranteed Transfer
Indicates MBC commitment to bus cycle completion.
Input to 82496 Cache Controller (pin N04)
Synchronous to ClK
Internal Pu II-up
Signal Description
The 82496 Cache Controller owns all bus cycles initiated by CADS# until the MBC accepts
ownership, and within this period, cycles may be aborted because of snoop write-backs. The
MBC signals its acceptance of ownership by driving BGT# active. CRDY# signals cycle
completion.
Once BGT# is asserted, the 82496 Cache Controller does not perform snoop lookups until the
end of the snooping window (until SWEND# is active). A snoop address is latched if
SNPSTB# is asserted between BGT# and SWEND#, but the snoop lookup does not begin until
the second CLK after SWEND# is sampled active by the 82496 Cache Controller.
When Sampled
The 82496 Cache Controller begins sampling the BGT# input after it asserts CADS#. BGT#
should be asserted prior to or with MEOC# for a given cycle.
BGT# is a "don't care" input after it has been recognized for a particular cycle and until
CRDY# (regardless of a pipelined CADS# issued before CRDY#). BGT# is ignored if there is
no outstanding CADS#. BGT# is also a "don't care" signal once a cycle started by CADS# is
aborted by a snoop and until a new CADS# is issued.
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