Intel 82496 CACHE CONTROLLER User Manual page 53

PINOUTS
Table 1-10. Pentium™ Processor CPU-Cache Chip Set Brief Pin Descriptions (Contd.)
Symbol Type Part Name and Function
The following Pentium processor pins are sampled during the falling
edge of RESET:
BUSCHK#, BRDYC#, CLRDRV: used to configure I/O buffers. FLUSH#,
FRCMC# and INIT: sampled when RESET transitions from high to low to
determine if tristate test mode or checker mode will be entered, or if BIST
will be run.
SCYC I CC The
Split Cycle
signal is asserted during misaligned LOCK transfers to
0
P
indicate that more than two cycles will be locked together. This signal is
defined for locked cycles only. It is undefined for cycles which are not
locked.
SEC2#
0
CC The 82496 Cache Controller drives the
2 lines per sector Optimized
I CS
Interface Configuration
signal during RESET to the 82491 Cache SRAM
to pass along lines/sector information. If active, SEC2# indicates 2 lines
per sector.
SEC2# shares pins with the 82496 Cache Controller and 82491 Cache
SRAM WBA signals.
SET[10:0]
I/O
CC See CFA[6:0].
SLFTST# I
CC
If the
82496 Cache Controller Self Test Configuration
signal is
sampled LOW (active) during the falling edge of RESET while MBALE is
HIGH (active), 82496 Cache Controller self-test is invoked.
SLFTST# shares a pin with the 82496 Cache Controller input signal
CRDY#.
SMI# I P The
System Management Interrupt
causes a system management
interrupt request to be latched internally. When the latched SMI# is
recognized on an instruction boundary, the processor enters System
Management Mode.
SMIACT#
0
P An active
System Management Interrupt Active
signal indicates that the
processor is operating in System Management Mode (SMM).
SMLN#
0
CC
Same Cache Line
indicates to the memory bus controller that the current
cycle accesses the same 82496 Cache Controller line as the previous
memory (not I/O) cycle. SMLN# is valid together with CADS# and can be
used to selectively activate SNPSTB# for other caches. For example,
SMLN# can prevent consecutive snoops to the same line.
SNPADS#
0
CC
Cache Snoop Address Strobe
functions exactly like CADS# but is
generated only on snoop write-back cycles. Because snoop write-back
cycles must be immediately serviced on the memory bus, the separate
address strobe eases memory bus controller (MBC) implementation.
When SNPADS# is active, the MBC aborts all pending cycles (ie. those for
which BGT# has not been issued; after BGT#, snoop lookups are
delayed). The 82496 Cache Controller may re-issue cycles following
snoop completion.
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