Read Only Accesses: Mro; Locked Accesses: Lock - Intel 82496 CACHE CONTROLLER User Manual

COMPONENT OPERATION
MWB/WT# pin LOW whenever the address corresponding to the line is referenced. Note that
using the PWT attribute in the CPU page table causes an entire page to be write-through; a
line in a write-through page is also write-through. The PWT attribute does not allow the
system designer to implement line-by-line write-through protocol. Write through cache
consistency protocol only uses S and I cache line states.
The Page Write Through attribute is driven by the processor's PWT output and corresponds to
a write through bit in the page table entry of a memory location's virtual address.
If
the PWT
bit is asserted when the CPU presents a memory address, the memory location will not be
cached in the exclusive or modified states in either the 82496 Cache Controller/82491 Cache
SRAM or the Pentium processor caches.
MWB/WT# is a 82496 Cache Controller input which connects to the memory bus controller or
to the bus itself. When MWB/WT# is low, it also prevents lines from being cached in exclusive
or modified states in either the 82496 Cache Controller/82491 Cache SRAM or the CPU
caches. MWB/WT# only affects the current access.
If
the Pentium processor PWT output is active or the 82496 Cache Controller MWB/WT#
input is low, the current line will never be placed into the exclusive or modified states. On a
linefill, the state of the line will always be shared. Note that if the 82496 Cache
Controller/82491 Cache SRAM already has an exclusive or modified copy of the line, PWT
has no effect on the cycle.
3.6.3.
Read Only Accesses: MRO#
The Memory Read Only input (MRO#) is driven by the memory bus to indicate that a memory
location is read-only.
When asserted during a read miss line fill, MRO# causes the current line to be placed in the
82496 Cache Controller/82491 Cache SRAM in the [S] state. MRO# also sets a read-only bit
in the cache tag.
On subsequent write hits to a read-only line, data is written to main memory without updating
the 82496 Cache Controller/82491 Cache SRAM line. The cached line remains in the [S] state
with the read-only bit set. Subsequent read hits to read-only data will not be cacheable in the
CPU cache.
The 82496 Cache Controller supports caching of Read-Only code lines in the CPU cache by
using the KEN# signal to the CPU. Read-only code (CD/C# low) is cached in the Pentium
processor by asserting KEN# to the CPU during a line fill. The Pentium processor
automatically invalidates cache lines in its code cache if they are written to.
If
KEN# is
deasserted to the'CPU, read only data will not be cached in the Pentium processor cache.
3.6.4.
Locked Accesses: LOCK#
The LOCK# signal is driven by the CPU to indicate that the requested cycle should lock the
memory location for an atomic memory access. Because locked cycles are used for inter-
processor and inter-task synchronization, all locked cycles must appear on the memory bus.
During locked write cycles, the 82496 Cache Controller/82491 Cache SRAM treats accesses as
write-through cycles. The 82496 Cache Controller/82491 Cache SRAM sends data to the
I
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