Intel 82496 CACHE CONTROLLER User Manual page 333

HARDWARE INTERFACE
5.2.2.138. TOO
TOO Test Data Output
Outputs serial test instructions and data.
Output from Pentium processor (pin S21). 82496 Cache Controller (pin DOS). and
82491 Cache SRAM (pin 84)
Synchronous to TCK
Signal Description
TDO is the serial output used to shift IT AG instructions and data out of the component. The
shifting of instructions and data occurs during the SHIFf-IR and SHIF-DR TAP controller
states, respectively. These states are selected using the TMS signal as described in the
testability chapter.
When not in the SHIFT-IR or SHIFT-DR state, IDO is driven to a HIGH impedance state to
allow connecting TDO of different devices in parallel.
When Driven
TDO is driven on the falling edge of TCK during the SHIFT-IR and SHIFf-DR TAP
controller states. At all other times TDO is driven to the HIGH impedance state.
Relation to Other Signals
Pin Symbol
Relation to Other Signals
TCK TOO is only driven when TMS and TCK have been used to select the SHIFT-IR or
SHIFT-DR states in the TAP controller.
TMS
TOO is only driven when TMS and TCK have been used to select the SHIFT-IR or
SHIFT-DR states in the TAP controller.
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