Intel 82496 CACHE CONTROLLER User Manual page 130

HARCWAREINTERFACE
Controller/82491 Cache SRAM requires four or eight transfers. The 82496 Cache
Controller/82491 Cache SRAM configuration determines whether the 82496 Cache
Controller/82491 Cache SRAM requires four or eight transfers.
The 82496 Cache Controller/82491 Cache SRAM services read and write hit cycles to the [E]
or [M] states and reads to the [S] state without MBC control. The MBC must be employed to
identify and control all other 82496 Cache Controller cycles. Table 5-1 lists all 82496 Cache
Controller cycles that require MBC control.
Table 5-1. Cycle Identification and Length
C
C C
R
M M M
Number of Number of
W 0
C
0
C
K
R
Memory
CPU
I I A Y A E 0 Bus Bus
R C C
S
C N
#
MBRCY#s'
# #
H
R
H
#
BROY#S
E
C
E
Cycle Type # #
Pentlum™ processor CPU-Cache Chip Set 0
1
0 1 0 0 1 82496 4 (processor
Cacheable Read Cache Line)
Controller
Line
Pentium Processor CPU-Cache Chip Set 0 0 0 1 0 0
x
82496 4 (processor
Cacheable Read Cache
Line)
Controller
Line
82496 Cache Controller/82491 Cache SRAM
0
x
1 1
0
0
x
82496 1
(not Pentium processor) Cacheable Read Cache
Controller
Line
82496 Cache Controller/82491 Cache SRAM
0
1
0 1 0 0 0 82496 1
(not Pentium processor) Cacheable Read Cache
Controller
Line
Non Cacheable Read (PCD=1 or Locked)
0
x x
1
1
x x
x
1
Non Cacheable Read (PCD=O) 0
x x
1
x
1
x x
1
82496 Cache Controller/82491 Cache SRAM 0
x x
0 0
x x
82496 0
Allocation (linetill) Cache
Controller
Line
Pentium Processor Memory Write or Locked 1
x
1 0 1
x x
1 0
Write
Replacement or Snoop Write Back 1
x x
0 0
x x
82496 0
Cache
Controller
Line
1/0
(CM/IO#=O) or Special Cycle
x x x
1 1
x x x
1
NOTE: A 82496 Cache Controller line is either 4 or 8 memory bus burst transfers. The number of transfers
is related to the configuration and depends upon the MTR4/8# input.
I
5-5