Deven - Device Enable; Deven - Device Enable Register - Intel I5-520E - DATASHEET ADDENDUM Datasheet

Processor Configuration Registers
6.1.1

DEVEN - Device Enable

B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
BIOS Optimal Default
Allows for enabling/disabling of PCI devices and functions that are within the processor.
The table below the bit definitions describes the behavior of all combinations of
transactions to devices controlled by this register. All the bits in this register are Intel
TXT Lockable.
Table 15.

DEVEN - Device Enable Register

Bit
31:15
14
13
12:12
11
10
9:9
8
7:4
3
2:2
1
0
April 2010
Document Number: 323178-002
Default
Access
Value
RO 0h
RW-L 0b
RW-L 0b
RO 0h
RW-L 0b
RW-L 0b
RO 0h
RW-L 1b
RO 0h
RW-L 1b
RO 0h
RW-L 1b
RO 1b
® TM
Intel Core i7-620LE/UE, i7-610E, i5-520E and Intel
0/0/0/PCI
54-57h
0000010Bh
RW-L; RO; RW
32 bits
000000h
RST/
PWR
Reserved
Core Reserved
Core PEG1 Enable (D6EN)
0 = Bus 0 Device 6 Function 0 is disabled
and hidden.
1 = Bus 0 Device 6 Function 0 is enabled
and visible.
Reserved
Core Reserved
Core Reserved
Reserved
Core Reserved
Reserved
Core Internal Graphics Engine Function 0
(D2F0EN)
0 = Bus 0 Device 2 Function 0 is disabled
and hidden
1 = Bus 0 Device 2 Function 0 is enabled
and visible
Reserved
Core PCI Express Port (D1EN)
0 = Bus 0 Device 1 Function 0 is disabled
and hidden.
1 = Bus 0 Device 1 Function 0 is enabled
and visible.
Core Host Bridge (D0EN)
Bus 0 Device 0 Function 0 may not be
disabled and is therefore hard wired to 1.
®
Celeron
Description
®
Processor P4500, P4505 Series
Datasheet Addendum
71