Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2887

• Poll DMA_STAT.RUN to wait for the status to reflect stop or idle state, and
• Write
DMA_CFG to the new configuration to begin the next work unit
In autobuffer-flow mode or for a list or array of descriptor sets without
to the DMA_CFG register to terminate the DMA transfer process. Configure the value of the DMA_CFG.EN bit in
this register to disable the DMA channel.
CAUTION: When the configuration disables a DMA channel, the DMA controller disables interrupt logic that is
based on work unit transitions. Be aware of the system environment and current actions, so that addi-
tional interrupts are not required from the DMA channel.
If disabled through DMA_CFG.EN in the middle of a transaction, the DMA channel completes any
CAUTION:
transactions that have begun and avoids generating bus errors. However, the channel considers the ac-
tion of re-enabling the DMA as a hard reset for all internal DMA channel components. Therefore, pay
attention to that particular action to avoid unexpected results.
DMA Channel Errors
When an error occurs, the DMA channel maintains all the state and register values that allow programs to diagnose
error causes more thoroughly. The greatest benefit to the programmer is to know exactly what operational state the
DMA channel was in at the exact moment the error occurred.
Take care to address the root cause of the error, whether or not the problem originated in the DMA channel. If not
properly resolved, the error can result in an additional error shortly after operations resume. The problem can cause
other errors elsewhere in the DMA channel or associated modules and circuitry. So, take care also to address those
potential problems. Ensure that all outstanding memory reads and writes are complete or cleared before resuming
DMA channel operation.
After addressing all issues and neutralizing all side effects of any errors, clear the DMA_STAT.ERRC status field and
restart the DMA channel by disabling then re-enabling the DMA channel through the DMA_CFG.EN bit.
The following sections describe the error types.
Status and Debug Errors
DMA channel error conditions can cause the DMA process to end abnormally. The DMA channel provides error
detection as a tool for system development and debug, helping to identify DMA-related programming errors. When
the DMA channel detects an error, the channel immediately stops and discards any returned memory-read transac-
tions. The DMA_STAT.RUN field of the DMA channel indicates the idle state after acknowledging all outstanding
memory transactions. In addition, the channel asserts an error interrupt request and updates the
DMA_STAT.IRQERR field. Also, the channel updates the DMA_STAT.ERRC field, indicating the error cause of
the first detected error. Unless the error occurs at the exact moment that modification of register values occurs, the
registers contain the error values.
All the DMA error interrupt requests are combined into a single shared interrupt request output. Combined error
signals require reading the
request to determine the DMA channel responsible for the generation of the interrupt.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
DMA_STAT register of each DMA channel associated with a combined error interrupt
descriptors, use an MMR write
DMA_CFG
Architectural Concepts
38–23