Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2793

Functional Description
Interpolation or Decimation Ratio (2): GDL = 16/f
SRC_FS_IP
Data Format
The ASRC Data Frame Format by Protocol figure shows the data input format for a frame (stereo data). The frame
format is valid for all protocols. For models which do not support matched phase mode the 8-bit data field is ignor-
ed.
Figure 36-3: ASRC Data Frame Format by Protocol
Operating Modes
The ASRC can operate in TDM, I
or can be used for moving the ASRC data to/from the internal memory.
2
In I S, left-justified and right-justified modes, the ASRCs operate individually. The serial data provided in the input
port is converted to the sample rate of the output port.
TDM Input Mode
In TDM input port, several ASRCs can be daisy-chained together and connected to the serial input port of a
SHARC processor or other processor (see the TDM Input/Output Modes figure). The ASRC IP contains a 64-bit
parallel load shift register. When the SRCx_FS_IP_I pulse arrives, each ASRC parallel loads its left and right data
into the 64-bit shift register. The input to the shift register is connected to SRCx_DATA_IP_I, while the output is
connected to SRCx_TDM_IP_O. By connecting the SRCx_TDM_IP_O to the SRCx_DATA_IP_I of the next
ASRC, a large shift register is created, which is clocked by SRCx_CLK_IP_I.
NOTE: The number of ASRCs that can be daisy-chained together is limited by the maximum frequency of
SRCx_CLK_xx_I, refer to the data sheet for exact values. For example, if the maximum frequency of
SRCx_CLK_xx_I is x MHz, and the output sample rate is fS, then number of ASRCs (n) that can be
connected in daisy chained fashion is: n 64 FS ≤ x MHz.
TDM Output Mode
As shown in the TDM Input/Output Modes figure, using the TDM output port several ASRCs can be daisy-chained
together and connected to the SPORT of this or another processor. The ASRC OP contains a 64-bit parallel load
shift register. When the SRCx_FS_OP_I pulse arrives, each ASRC loads its left and right data into the 64-bit shift
register. The input to the shift register is connected to SRCx_TDM_OP_I, and the output is connected to
36–6
LEFT-JUSTIFIED, I 2 S, AND TDM MODES
AUDIO DATA LEFT CHANNEL, MATCHED-PHASE
24 BITS DATA, 8 BITS
MSB (BIT-63)
MATCHED-PHASE AUDIO DATA LEFT CHANNEL,
DATA, 8 BITS 16 BITS - 24 BITS
2
S, left-justified, right-justified, and bypass modes. The serial ports of the process-
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
+ 32/f × f /f
S_IN S_IN S_IN
AUDIO DATA RIGHT CHANNEL,
24 BITS
RIGHT-JUSTIFIED MODE
MATCHED-PHASE AUDIO DATA RIGHT CHANNEL,
DATA, 8 BITS
seconds for SRC_FS_OP <
S_OUT
MATCHED-PHASE
DATA, 8 BITS
LSB (BIT-0)
16 BITS - 24 BITS