Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2904

DMA Channel Programming Model
7. Write the DMA_XCNT
ADDITIONAL INFORMATION:
entire work unit.
8. Write the
DMA_XMOD
ADDITIONAL INFORMATION: For a linear buffer transfer, determine the value in
lected DMA_CFG.MSIZE. This register is always specified in the number of bytes.
9. Write the DMA_CFG
channel.
ADDITIONAL INFORMATION: The DMA_CFG.FLOW bit must be set for stop mode. The
DMA_CFG.WNR bit must be configured for memory read operation. The DMA_CFG.PSIZE bits must be
configured to a value no larger than the supported bus width of the peripheral DMA bus.
• The DMA_CFG.SYNC bit can be configured to control DMA completion notification timing.
• Interrupts and triggers also can be configured at this step, depending on requirements. The interrupts and
triggers are enabled within the destination DMA channel configuration.
The memory read DMA transfer begins.
10. Write the DMA_CFG
DMA channel.
ADDITIONAL INFORMATION: The DMA_CFG.FLOW bit must be set for stop mode. The
DMA_CFG.WNR bit must be configured for memory write operation. The DMA_CFG.PSIZE bits must be
configured to a value no larger than the supported bus width of the peripheral DMA bus. This value must also
match the value written for the source DMA channel configuration.
• Interrupts and triggers also can be configured at this step depending on requirements.
The memory write DMA transfer begins.
Both memory DMA channels are now running and the data is transferred from the source address to the destination
address. The DMA channel enters the IDLE state upon completion of the work unit.
Programming Concepts
Using the features, operating modes, and event control for the DMA channel to their greatest potential requires an
understanding of some DMA channel-related concepts.
Synchronization of Software and DMA
A critical element of software DMA management is the synchronization of DMA work unit completion with soft-
ware. This synchronization can be achieved using DMA channel interrupt request and trigger events and using a
poll of the status bits of these events within the DMA channel registers, or combining these techniques. Processor
polling of DMA address/count/status for completion is not a recommended programming practice. The
38–40
register of the destination DMA channel based on the calculated DMA_CFG.MSIZE.
DMA_XCNT
register of the destination DMA channel.
register of the source DMA channel with DMA_CFG.EN configured to enable the DMA
register of the destination DMA channel with DMA_CFG.EN configured to enable the
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
is the number of DMA_CFG.MSIZE transfers to make up the
DMA_XMOD from the se-